Physical Design Engineer, Custom Datapath
Job Summary
Job Description
- 10+ years ASIC physical design experience
- Experience with advanced process nodes
- Proficiency in EDA CAD tools (Tcl, GUI)
- Collaboration with front-end and back-end teams
- Power optimization expertise
- Master's degree in relevant field
- Experience in full physical signoff stack
- Custom physical design experience (datapath, standard cell, SRAM/RF)
- Experience leading PD-aware design changes
- Familiarity with front-end design
5 skills required
Job Details
Minimum qualifications:
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
- 10 years of experience in ASIC physical design and methodologies in advanced process nodes.
- Experience driving place and route on designs using industry standard EDA CAD tools (including command execution, debugging, and custom technique development via Tcl or GUI).
Preferred qualifications:
- Master's degree in Computer Science, Electrical Engineering, Computer Engineering, a related technical field, or equivalent practical experience
- Experience in the complete physical signoff stack, including timing, PDV, EMIR, package concerns, and power.
- Experience with custom physical design, which may include custom datapath design, standard cell design, SRAM/RF design, and “relative placement” design.
- Experience measuring and optimizing overall design power.
- Familiarity with front-end design and experience leading “PD-aware” design changes to improve PPA or re-use.
About the job
In this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.
As a Custom Datapath Physical Design Engineer on the Chip Implementation team, you will work on the implementation of ASICs in advanced technology nodes. You will use your expertise in custom design and custom design tools to improve the efficiency of the next generation of our chips, unlocking design efficiency that is not attainable with traditional approaches. You will work closely with front-end designers and back-end designers to integrate your ideas into our flows and designs.
The ML, Systems, & Cloud AI (MSCA) organization at Google designs, implements, and manages the hardware, software, machine learning, and systems infrastructure for all Google services (Search, YouTube, etc.) and Google Cloud. Our end users are Googlers, Cloud customers and the billions of people who use Google services around the world.
We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including Google Cloud’s Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers.
The US base salary range for this full-time position is $183,000-$271,000 + bonus + equity + benefits. Our salary ranges are determined by role, level, and location. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.
Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about .
Responsibilities
- Work closely with front-end and back-end design teams to develop fully-custom or semi-custom datapath-based approaches to silicon design to maximize PPA.
- Integrate these flows with the greater PD flows while minimizing integration challenges.
- Measure and quantify costs and benefits of this approach for different designs and make clear ROI-based recommendations to the project.
- Work closely with RTL designers and inform design decisions to optimize PPA and enable effective datapath-based design, with a particular focus on power optimization.
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About The Company
A problem isn't truly solved until it's solved for all. Googlers build products that help create opportunities for everyone, whether down the street or across the globe. Bring your insight, imagination and a healthy disregard for the impossible. Bring everything that makes you unique. Together, we can build for everyone.
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