Senior Engineer II - ASIC Design

23 Hours ago • 7 Years +

Job Summary

Job Description

The Senior Engineer II - ASIC Design will perform physical design and verification tasks across projects in advanced process nodes. They will manage project-specific ASIC development flow setup and maintenance. Responsibilities include floor-planning, place and route, CTS, timing closure, IR/EM analysis, LEC for block level and full chip flat/hierarchical designs, and coordinating full chip physical design and verification activities. They will also handle physical verification tasks like creating setups and scripts for DRC, LVS, DFM, Antenna and density checks, report generation, analysis, debugging, and implementing fixes, ensuring correct IP and pad-ring integration and mentoring junior PD/PV team members. The role reports to the ASIC Design Director.

Must have:

7+ Years of experience in ASIC/ SoC Physical Design.
Experience in advanced FinFET node designs.
Experience with Cadence PnR/STA tools and Calibre.
Good scripting/automation skills is a must.
B. Tech /M. Tech in Electronics Engineering.

Perks:

Competitive Compensation Package
Restricted Stock Units (RSUs)
Hybrid Working Model
Provisions to pursue advanced education from Premium Institute, eLearning content providers.
Medical Insurance and a cohort of Wellness Benefits

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Job Details

The Opportunity

We're looking for the Wavemakers of tomorrow.

Alphawave Semi enables tomorrow’s future by accelerating the critical data communication at the heart of our digital world – from seamless video streaming to AI to the metaverse and much more. Our technology powers product innovation in the most data-demanding industries today, including data centers, networking, storage, artificial intelligence, 5G wireless infrastructure, and autonomous vehicles. Customers partner with us for mission-critical data communication, our innovative technologies, and our proven track record. Together, we enable the next generation of digital technology.

What You'll Do:

Perform hands-on physical design and physical verification tasks across projects in advanced process nodes.

Manage project-specific ASIC development flow setup and maintenance.

Physical design tasks include floor-planning, place and route, CTS, timing closure, IR/EM analysis, and LEC for block level and full chip flat/hierarchical designs. Coordinate full chip physical design and verification activities.

Physical verification tasks include creating setup and scripts for DRC, LVS, DFM, Antenna and density checks, report generation, analysis, debugging, and implementing fixes in the physical design database.

Ensure correct IP and pad-ring integration in block and flat designs.

Mentor junior PD/PV team members and oversee their tasks.

You will be reporting to ASIC Design Director.

What You'll Need:

Minimum 7+ Years of experience in ASIC/ SoC Physical Design.

Skills – have working experience in advanced FinFET node designs.

Experience with Cadence PnR/STA tools and Calibre; good scripting/automation skills is a must.

Education – B. Tech /M. Tech in Electronics Engineering.

"Hybrid work environment"

As part of our commitment to the well-being and satisfaction of our employees, we have designed a comprehensive benefits package that includes:

Competitive Compensation Package

Restricted Stock Units (RSUs)

Hybrid Working Model

Provisions to pursue advanced education from Premium Institute, eLearning content providers.

Medical Insurance and a cohort of Wellness Benefits

Equal Employment Opportunity Statement

Alphawave Semi is an equal opportunity employer, welcoming all applicants regardless of age, gender, race, disability, or other protected characteristics. We value diversity and provide accommodations during the recruitment process.