Senior Network Design Verification Engineer
Job Summary
Job Description
- Bachelor's degree in EE or equivalent
- 5+ years verifying digital designs (RTL, SystemVerilog)
- Experience with networking (RDMA, packet processing)
- SystemVerilog or Specman/E experience
- Constrained-random verification
- Coverage closure
- Experience with IP components/interconnects
- TCP/IP, Ethernet, PCIe, DRAM, NoC knowledge
- Performance estimation & simulation
- ASIC verification & standard interfaces
- Formal verification (SVA)
4 skills required
Job Details
Minimum qualifications:
- Bachelor's degree in Electrical Engineering or equivalent practical experience.
- 5 years of experience verifying digital reasoning at Register-Transfer Level (RTL) using SystemVerilog or Specman/E for Field Programmable Gate Arrays (FPGAs) or ASIC.
- Experience working with design networking like Remote Direct Memory Access (RDMA) or packet processing and system design principles for low latency, high throughput, security, and reliability.
- Experience in creating and using verification components and environments in standard verification methodology.
Preferred qualifications:
- Experience in verifying digital systems using standard Internet Protocol (IP) components or interconnects (e.g., microprocessor cores, hierarchical memory subsystems).
- Experience in Transmission Control Protocol (TCP), IP, Ethernet, PCIE and Dynamic Random-Access Memory (DRAM), Network on Chip (NoC) principles and protocols.
- Experience in estimating performance by analysis, modeling, and network simulation in defining and driving performance test plans.
- Experience with verification techniques, and the full verification life cycle.
- Experience with performance verification of ASICs and ASIC components.
- Experience with ASIC standard interfaces and memory system architecture.
About the job
In this role, you will work as part of a Research and Development team. You will build verification components, constrained-random testing, system testing, and verification closure. You will verify digital designs and collaborate with design and verification engineers in projects and perform direct verification. You will build efficient and effective constrained-random verification environments that exercise designs through their corner-cases and expose all types of bugs. You will manage the full lifecycle of verification which can range from verification planning, test execution or collecting, and closing coverage.
The ML, Systems, & Cloud AI (MSCA) organization at Google designs, implements, and manages the hardware, software, machine learning, and systems infrastructure for all Google services (Search, YouTube, etc.) and Google Cloud. Our end users are Googlers, Cloud customers and the billions of people who use Google services around the world.
We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including Google Cloud’s Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers.
Responsibilities
- Plan the verification of digital design blocks by understanding the design specification and interacting with design engineers to identify important verification scenarios.
- Create and enhance constrained-random verification environments using SystemVerilog or formally verify designs with Strategic Value Add (SVA) and industry leading formal tools.
- Identify and write all types of coverage measures for stimulus and corner-cases.
- Debug tests with design engineers to deliver functionally correct design blocks.
- Close coverage measures to identify verification holes and to show progress towards tape-out.
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