Design Verification Engineer

As a Design Verification Engineer, you will ensure bug-free silicon for a part of the SoC/IP. You will develop detailed test and coverage plans based on micro-architecture and verification methodologies suitable for the IP, ensuring a scalable and portable environment. This includes developing the verification environment, including stimulus, checkers, assertions, trackers, and coverage. You will create verification plans for all features, execute them, and debug test failures. You will also develop block, IP, and SoC level test benches, tracking and reporting progress using metrics like bugs and coverage.