Physical Design and Implementation Engineer, CPU

This Physical Design and Implementation Engineer role at Google involves developing all aspects of ASIC RTL2GDS implementation for high PPA designs. Responsibilities include managing block and full-chip level physical implementation and QoR (power, timing, area). The ideal candidate will have at least one year of experience in Physical Design and experience with two chip tape outs. The team focuses on creating custom silicon solutions for Google's direct-to-consumer products, contributing to innovation and delivering high-performance, efficient hardware. The role requires expertise in ASIC implementation, optimizing power, timing, and area, contributing to the next generation of hardware experiences. The work contributes to Google's mission of making information universally accessible and useful.