ASIC Design Engineer Silicon

1 Month ago • 2 Years + • Research & Development

Job Summary

Job Description

This ASIC Design Engineer role at Google involves developing custom silicon solutions for direct-to-consumer products. Responsibilities include defining microarchitecture details (interface protocols, block diagrams, data flow, pipelines), RTL development (SystemVerilog) and debugging simulations. The role also encompasses RTL quality checks (Lint, CDC, Synthesis, UPF), participation in synthesis, timing/power estimation, and FPGA/silicon bring-up. The ideal candidate possesses experience with digital design in ASIC, RTL design using Verilog/System Verilog and microarchitecture, ARM-based SoCs, interconnects, ASIC methodology, and scripting languages like Python or Perl. Experience with low power estimation, timing closure, synthesis, and RTL quality checks (Lint, CDC, RDC) is preferred.
Must have:
  • Bachelor's degree in related field
  • ASIC digital design experience
  • RTL design (Verilog/SystemVerilog)
  • ARM-based SoCs experience
  • Scripting language (Python/Perl)
Good to have:
  • Master's/PhD in related field
  • 2+ years IP design experience
  • Low power estimation experience
  • Timing closure & synthesis experience
  • RTL quality checks (Lint, CDC, RDC)

Job Details

Minimum qualifications:

  • Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
  • Experience with digital design in ASIC.
  • Experience with RTL design using Verilog/System Verilog and microarchitecture.
  • Experience with ARM-based SoCs, interconnects and ASIC methodology.
  • Experience with a scripting language like Python or Perl.

Preferred qualifications:

  • Master's degree or PhD in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
  • 2 years of industry experience with IP design.
  • Experience with methodologies for low power estimation, timing closure, synthesis.
  • Experience with methodologies for RTL quality checks (e.g., Lint, CDC, RDC).

About the job

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.

Responsibilities

  • Define microarchitecture details such as interface protocol, block diagram, data flow, pipelines, etc.
  • Perform RTL development (SystemVerilog), debug functional/performance simulations.
  • Perform Register-Transfer Level (RTL) quality checks including Lint, Clock Domain Crossing (CDC), Synthesis, Unified Power Format (UPF) checks.
  • Participate in synthesis, timing/power estimation and Field Programmable Gate Array (FPGA)/silicon bring-up.

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