Jobs

Scholarships

Courses

Companies

Placements

Community

Home >

Jobs >

Chassis Power Architect, Silicon

Chassis Power Architect, Silicon

2 Hours ago • 5 Years + • Research & Development

About the job

2 skills required for this role

Test your skills to join the top 1% applicants for this job

innovation

cross-functional

Job Description

The Chassis Power Architect, Silicon at Google will drive architecture and microarchitecture development for next-generation power management controllers, from specification to SoC deployment. This role involves developing power optimization methods for various chassis IPs, influencing power methodologies for SoC design and implementation, and creating innovative plans for power optimization across different levels. Collaboration with cross-functional teams is crucial, including work on power management IPs, clock, reset, and power control strategies. The candidate will guide pre-silicon power modeling and post-silicon power correlation efforts, working with system and chipset architects on power planning and management. The primary focus will be on next-generation power management controllers, chassis power architecture/microarchitecture, and power vs. performance tradeoffs for various SoC and chassis components.

Must have:

Bachelor's degree in EE/CS or related field
5+ years experience in power enhancement
Experience with power management IPs
Expertise in low power design techniques
Proficiency in Verilog, SystemVerilog, RTL, SPICE simulations

Good to have:

Experience with EDA tools (Conformal LP, Power-Artist, etc.)
Post-silicon power calibration and debug experience
Full chip power design and analysis understanding
UPF/CPF experience
Multi-voltage domains and power gating experience

Not hearing back from companies?

Unlock the secrets to a successful job application and accelerate your journey to your next opportunity.

Minimum qualifications:

Bachelor's degree in Electrical Engineering, Computer Science, a related field, or equivalent practical experience.
5 years of experience in power enhancement workflow and techniques.
Experience with power management IPs.

Preferred qualifications:

Experience in low power design including UPF/CPF, multi-voltage domains, power gating, and on chip power management IP design.
Experience in Verilog, SystemVerilog, RTL and gate-level SPICE simulations, and statistical SPICE models.
Experience using EDA tools like Conformal LP, Power-Artist, DC/RC, PT/PTPX, Incisive/VCS.
Experience in post-silicon power calibrations and debug.
Experience in design and analysis of full chip power with an understanding of clock, reset, and power sequencing interactions.

About the job

Be part of a diverse team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

As part of the Google Silicon Platform IP Architecture team, you will collaborate with SoC and IP hardware architects and Design Engineers to drive next generation power management controller and chassis power optimization in advanced technology nodes, focused on Google Tensor SoC and other associated products.

In this role, you will define power management controller and it’s deployment across SoC, power optimization methods, chart power roadmaps for Chassis IPs, propose power optimization plans in consultation with cross-functional teams, guide pre-silicon power modeling and post-silicon power correlation efforts, and interface with system and chipset power architects on both power planning and power management strategies. Your primary focus will be on our next-generation power management controller, chassis power architecture/microarchitecture and power vs performance tradeoffs for various SoC and chassis components.

Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.

Responsibilities

Drive architecture and microarchitecture development for next generation power management controllers all the way from specification to SoC deployment.
Come up with Power optimization methods for various chassis IP’s.
Influence Power methodology for design, verification and implementation of deep submicron SoCs.
Develop innovative plans to achieve power optimization from circuit to system level.
Influence generic power management IPs to drive clock, reset, and power controls.

View Full Job Description

Upload your resume, increase your shortlisting chances by 80%

About The Company

Google

1686 Active Jobs

A problem isn't truly solved until it's solved for all. Googlers build products that help create opportunities for everyone, whether down the street or across the globe. Bring your insight, imagination and a healthy disregard for the impossible. Bring everything that makes you unique. Together, we can build for everyone.