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Senior Physical Design Engineer, Mixed Signal, Silicon

New Taipei City, Taiwan (On-site)

Senior Physical Design Engineer, Mixed Signal, Silicon

3 Days ago • 5 Years + • Research & Development

About the job

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Job Description

Google is seeking a Senior Physical Design Engineer, Mixed Signal, Silicon to join their team in New Taipei City, Taiwan. This role involves generating high-quality Place and Route (PnR) results for digital blocks, ensuring Design Rule Checking (DRC) and Layout Versus Schematic (LVS) signoff. Responsibilities include monitoring block timing using STA tools, analyzing designs for power, area, and performance trade-offs, and applying engineering best practices. The engineer will also analyze power integrity (EMIR), implement fixes, and collaborate with front-end designers and back-end integration engineers. Experience with PnR/APR, STA, EMIR, DRC tools, scripting languages (Tcl, Python), and low-power design techniques is required. The ideal candidate will possess knowledge of advanced ECO techniques, synthesis/optimization methodologies, AMS/DMS design integration, and scaled CMOS processes.

Must have:

5+ years physical design experience
PnR/APR, STA, EMIR, DRC expertise
Scripting (Tcl, Python)
High-quality PnR results
Timing analysis & optimization

Good to have:

Low-power design techniques (UPF)
Advanced ECO techniques
Synthesis & optimization methodologies
AMS/DMS design integration
FinFET experience
Git knowledge

Minimum qualifications:

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
5 years of experience in physical design.
Experience with PnR/APR, STA, EMIR, and DRC tools/flows working on synthesized designs.
Experience in one or more scripting languages (e.g., Tcl, Python, etc.).

Preferred qualifications:

Experience with low-power design techniques such as multiple power domains, power switches, level shifting, isolation, and dynamic voltage/frequency scaling using Unified Power Format (UPF).
Experience with advanced Engineering Change Order (ECO) techniques including full layer and metal-only changes.
Experience with synthesis and optimization methodologies.
Experience with Analog and Mixed Signal (AMS/DMS) design integration including custom routing, shielding, and analog macro integration.
Experience working with scaled Complementary Metal Oxide Semiconductor (CMOS) processes (e.g., FinFET).
Knowledge of version control systems such as Git.

About the job

Be part of a diverse team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.

Responsibilities

Generate high-quality Place and Route (PnR) results for one or more digital blocks, including Design Rule Checking (DRC) and Layout Versus Schematic (LVS) signoff, working closely with front-end designers and back-end physical design integration engineers.
Monitor the timing of blocks closely with modern Static Timing Analysis (STA) tools and techniques, and recommend design enhancements when an issue arises.
Analyze designs based on key metrics, including power, area, and performance trade-off.
Apply engineering best practices (e.g., code review, testing, refactoring) to the design and implementation of ASIC blocks.
Analyze power integrity Electromagnetic migration and IR drop (EMIR) of blocks and implement fixes once issues are identified.

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About The Company

Google

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A problem isn't truly solved until it's solved for all. Googlers build products that help create opportunities for everyone, whether down the street or across the globe. Bring your insight, imagination and a healthy disregard for the impossible. Bring everything that makes you unique. Together, we can build for everyone.