Jobs

Scholarships

Courses

Companies

Placements

Community

Home >

Jobs >

Senior RTL Design Engineer, Google Cloud

Tel Aviv District, Israel (On-site)

Senior RTL Design Engineer, Google Cloud

1 Hour ago • 5 Years + • Research & Development

About the job

4 skills required for this role

Add these skills to join the top 1% applicants for this job

python

perl

fpga

innovation

Job Description

This Senior RTL Design Engineer role at Google Cloud involves designing custom silicon solutions for Google's consumer products. Responsibilities include leading complex ASIC subsystems, defining high-performance hardware/software interfaces, writing micro-architecture and design specifications, and collaborating with various engineering teams (software, verification, physical design) to ensure design completion and performance. The role requires ASIC design expertise, from specification to production, using Verilog and working with high-speed interfaces like PCIe and InfiniBand. The engineer will contribute to the SoC design cycle, from architecture definition to RTL coding and simulations.

Must have:

5+ years RTL development (Verilog)
Experience with PCIe, InfiniBand
Micro-architecture, design, verification
Logic synthesis, timing closure
ASIC subsystem leadership
Collaboration with various engineering teams

Good to have:

Scripting (Python/Perl)
Arithmetic units, bus architectures
High-performance/low-power design
FPGA, emulation, SoC architecture
Assertion-based formal verification

Minimum qualifications:

Bachelor's degree in Electrical Engineering or equivalent practical experience.
5 years of experience with RTL development for ASIC subsystems using Verilog.
Experience with speed interfaces such as PCIe, InfiniBand, and their low latency, security, and reliability principles.
Experience with micro architecture, design, verification, logic synthesis, and timing closure.

Preferred qualifications:

Experience with scripting languages (e.g., Python or Perl).
Knowledge of arithmetic units, bus architectures, processor design, accelerators, or memory hierarchies.
Knowledge of high performance and low power design techniques.
Knowledge of FPGA, emulation platforms, and SoC architecture.
Knowledge of assertion-based formal verification.

About the job

Be part of a diverse team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

In this role, you will use Application-Specific Integrated Circuit (ASIC) design to be part of a team that creates the System on a Chip (SoC) design cycle from start to finish. You will collaborate with design and verification engineers in projects, creating architecture definitions with Register-Transfer Level (RTL) coding, and running block level simulations. You will contribute in ASIC designs from design specification to production. You will collaborate with members of architecture, software, verification, power, timing, synthesis and more to specify and deliver high quality SoC/RTL. You will also solve technical problems with innovative micro-architecture and practical logic solutions, and evaluate design options with performance, power, and area in mind.

Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.

Responsibilities

Lead a complex ASIC subsystem.
Understand how it interacts with software and other ASIC subsystems to implement groundbreaking data center.
Define high-performance hardware/software interfaces. Write micro architecture and design specifications.
Define efficient micro-architecture and block partitioning/interfaces and flows.
Collaborate closely with software, verification, and physical design stakeholders to ensure the designs are complete, correct, and performant.

View Full Job Description

Upload your resume, increase your shortlisting chances by 80%

About The Company

Google

2744 Active Jobs

A problem isn't truly solved until it's solved for all. Googlers build products that help create opportunities for everyone, whether down the street or across the globe. Bring your insight, imagination and a healthy disregard for the impossible. Bring everything that makes you unique. Together, we can build for everyone.