SoC Design Engineer, Cloud
Job Summary
Job Description
- RTL coding (Verilog/SystemVerilog)
- Experience with EDA tools
- SoC IP integration
- System-on-a-Chip (SoC) sign-off
- Digital design fundamentals
- Master's degree in relevant field
- Experience architecting RTL solutions
- Experience with AXI
- Scripting languages (Tcl, Python, Perl)
- Clock/Reset Domain Crossing, RTL Linting
3 skills required
Job Details
Minimum qualifications:
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
- 1 year of experience with RTL coding using Verilog/SystemVerilog.
- Experience with industry-standard tools, languages and methodologies relevant to the development of silicon-based ICs and chips such as: EDA tools for simulation or synthesis.
Preferred qualifications:
- Master's degree in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
- Experience architecting RTL solutions employing software based construction, instantiation, customization and generation of RTL.
- Experience with SoC implementation standards and interfaces (i.e., AXI).
- Experience with scripting languages (i.e. Tcl, Python or Perl).
- Experience with Clock Domain Crossing, Reset Domain Crossing, RTL Linting and Logic Equivalence Checking.
- Understanding of digital design fundamentals, including synchronous and asynchronous logic, state machines, and bus protocols.
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
In this role, you will be part of a group of engineers to uplift an existing on-chip connectivity solution into one that will be programmatically assembled, instantiated and optimized. Your expertise will inform the architecture and micro-architectural modifications of the solution to enable discrete blocks of functionality to be assembled and instantiated by software to provide customized and flexible implementations. You will work in providing users the ability to customize the performance, power and area of the solution based on the needs of the system. You will also work within the team to manage SoC IP integration and participate in System-on-a-Chip (SoC) level sign-off activities.
The ML, Systems, & Cloud AI (MSCA) organization at Google designs, implements, and manages the hardware, software, machine learning, and systems infrastructure for all Google services (Search, YouTube, etc.) and Google Cloud. Our end users are Googlers, Cloud customers and the billions of people who use Google services around the world.
We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including Google Cloud’s Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers.
The US base salary range for this full-time position is $113,000-$161,000 + bonus + equity + benefits. Our salary ranges are determined by role, level, and location. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.
Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about .
Responsibilities
- Develop strategies for system segmentation to enable programmatic assembly of custom solutions based on user design intent.
- Design RTL architecture of system to allow for automated optimization of RTL performance, power and area based of solution requirements.
- Design and implement RTL code for various digital blocks, including complex control logic, and on-chip data paths.
- Participate in SoC IP integration and sign-off activities.
- Contribute to the development and improvement of design flows, tools and methodologies.
Similar Jobs
Dream Sports
PwC
ByteDance
N-iX
NVIDIA
Get notifed when new similar jobs are uploaded
Similar Skill Jobs
Activision
Microsoft
Rockstar Games
ByteDance
Get notifed when new similar jobs are uploaded
Jobs in Sunnyvale, California, United States
ByteDance
Inworld AI
Netflix
Get notifed when new similar jobs are uploaded
Research & Development Jobs
NVIDIA
Krafton
NVIDIA
Get notifed when new similar jobs are uploaded
About The Company
A problem isn't truly solved until it's solved for all. Googlers build products that help create opportunities for everyone, whether down the street or across the globe. Bring your insight, imagination and a healthy disregard for the impossible. Bring everything that makes you unique. Together, we can build for everyone.
Get notified when new jobs are added by Google
