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Sr. Staff Software Engineer – Compiler

Texas, United States (On-site)

Sr. Staff Software Engineer – Compiler

2 Months ago • 5-15 Years

About the job

7 skills required for this role

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cpp

linux

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scalability

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Job Description

We're seeking a skilled Sr. Staff Compiler Expert to build a high-performance MIPS RISC-V compiler. You'll develop GNU toolchains, manage code branches, run regression tests, build and release toolchains, support new instructions, add optimizations, and analyze benchmark performance. Must have strong compiler development, RISC-V architecture, and optimization experience.

Must have:

GNU Toolchains
Compiler Optimization
RISC-V Architecture
Problem Solving

Good to have:

LLVM
FPGA Platforms
Benchmark Analysis
Linux Kernel

Perks:

Unlimited Growth
Industry Leading

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We are seeking a highly skilled Sr. Staff Compiler Expert to join our team and help us build a high-performance compiler for MIPS RISC-V microprocessors. In this role you will be involved in all aspects of toolchains, from compilers, assemblers, linkers, debuggers, C/C++ libraries, to emulators. You will also work directly with customers at all stages, including onboarding, support, and troubleshooting.

We are building toolchains that will allow our customers to obtain the highest performance from hardware and software synergy.

If you are an innovative problem solver with a deep understanding of compiler toolchain development, microprocessor architecture and application performance, and a passion for improving computers, we want to hear from you!

You will:

Develop GNU toolchains that include GCC, Binutils, GDB, Glibc, and Newlib.
Obtain code base from open-source projects and manage branches for development.
Forward-port or back-port patches to different branches.
Run compiler regression tests via Dejagnu on QEMU emulators.
Build and release GNU toolchains to internal and external customers.
Support new RISC-V instructions in GNU toolchains.
Add processor pipeline descriptions to GCC.
Add target-independent and target-dependent optimizations to GCC.
Run benchmarks that include Dhrystone, Coremark, Coremark Pro, and SPEC benchmarks on FPGA platforms.
Analyze and improve benchmark performance on Linux and bare metal.
Debug applications and Linux kernel.
Develop LLVM to have similar features and optimizations.

Ideally, you’ll have:

Proven experience developing with GNU toolchains.
Experience in compiler optimizations.
Knowledge and experience with RISC microprocessor architectures and simulators.
Excellent problem-solving skills and ability to troubleshoot complex technical issues.
Familiarity with the extension architectures, APIs, and best practices.
Excellent communication and collaboration abilities.
Passion for improving software performance.
Bachelor's with 12-15 years’ experience - Masters with 8-11 years of experience - PhD + 5-7 years of work experience

Here’s what you can expect from us:

At MIPS, you’ll be a member of a fast-growing team of technologists that are creating the industry’s highest performance RISC-V processors. Small teams that are part of a non-compartmentalized structure – you’ll be able to understand and have an impact on the bigger picture. A great deal of autonomy, with support from some of the industry’s most experienced CPU engineers. An unlimited growth path – with the right skills, you can decide where you want to expand and grow in your role at MIPS. The opportunity to learn a great deal about the blossoming RISC-V architecture in cutting edge applications with industry leading customers.

At MIPS we provide meaningful benefits programs and products to our associates and their families. MIPS offers a competitive benefits package that includes medical, dental, vision, retirement savings, and paid leave!

More about us:

MIPS is well-known as a microprocessor pioneer, having led the way in RISC-based computing to enable faster and more power efficient semiconductors for a wide range of applications from consumer electronics to networking and communications. More than 30 years after the introduction of the original MIPS RISC architecture, MIPS processors have shipped into billions of consumer and enterprise products.

Today, MIPS is once again leading a RISC revolution as we build on our deep roots to accelerate the RISC-V architecture for high-performance applications. We are focused on delivering our first RISC-V products: the MIPS eVocore processors, which provide a new level of scalability for high-performance heterogeneous computing. Because of our RISC heritage, deep engineering expertise, and proven technologies, MIPS can accelerate development and deployment of RISC-V based solutions.

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