Analog IC Design Intern - Ph. D

3 Days ago • Upto 1 Years

About the job

SummaryBy Outscal

This internship is for PhD students with proven experience in analog IC design. You will be responsible for design and verification of high-performance broadband analog circuits, including TIAs, linear regulators, and AGC loops. Experience with SiGe BiCMOS and CMOS technologies is a plus.

About Marvell

Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, automotive, and carrier architectures, our innovative technology is enabling new possibilities. 

At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. 

Your Team, Your Impact

Our world class group leverages our core competencies in advanced circuit design to solve the world’s ever-increasing desire to transmit more data for less power with fewer errors. We are continually first to market in Data Center, Metro and Long-Haul applications. As a member of the design group, this intern will be responsible for design and validation of FET and BiCMOS circuits for high-speed broadband ICs that serve these applications.

What You Can Expect

Our team is seeking an Analog Design Engineer intern to contribute to the development of multi-tens of GHz Transimpedance Amplifiers TIAs. These optical interface chips are tightly coupled with our high-performance equalizers. The results of our innovative designs have made our TIAs best in class for coherent long-haul and metro systems as well as PAM4 data center systems.

In this role you will be responsible for:

  • Active circuit design and verification of High-performance broadband analog circuits for optical front-end receivers.
  • Working with various other analog circuits including linear regulators, AGC loops, current/voltage sensors, bandgaps etc. Working with various technologies including SiGe BiCMOS and CMOS.
  • Working in a team to deliver full-chip TIA solutions.
  • Developing transmission line structures and other millimeter wave structures to enable higher performance than would normally be achievable.
     

What We're Looking For

  • Must be currently enrolled at an accredited college or university pursuing a Ph. D in relevant Electrical / Computer Engineering related program OR combination of MS coursework and relevant experience
  • Proven experience in analog IC design including chip tape-out and lab measurement is a plus
  • Solid experience using EDA CAD tools and performing Analog Custom Layout
  • Deep understanding of fundamentals, including detailed transistor level design, device physics, control/Feedback loop stability analysis
  • Experience in using different technologies (SiGe BiCMOS is a plus)
  • A team-player, strong communication, presentation, and documentation skills
  • Experience in at least one of the following areas is a plus: Transimpedance amplifier stages, variable Gain Broadband amplifiers, matched Transmission line drivers, CTLE design, AGC loop design, high precision analog circuits (Including linear regulators, current sensors, bandgaps, and DAC/ADC)

Expected Base Pay Range (USD)

27 - 54, $ per hour.

The successful candidate’s starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. The expected base pay range for this role may be modified based on market conditions.

Additional Compensation and Benefit Elements 

For Internship roles, we are proud to offer the following benefits package during the internship - medical, dental and vision coverage or opt-out credit, perks and discount programs, virtual fitness subsidy, wellness & mental health support including coaching and therapy, paid holidays, paid volunteer days and paid sick time. Additional compensation maybe available for intern PhD candidates.

This role is eligible for our hybrid work model in which you will be able to split time between working from home and on-site in a Marvell office.

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.

Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at TAOps@marvell.com.

#LI-SC1
$27 - $54/yr (Outscal est.)
$40.5/yr avg.
Santa Clara, California, United States

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