ASIC Engineer, IP Design
Job Summary
Job Description
- 5+ years RTL design (Verilog/SystemVerilog)
- 5+ years ARM-based SoC experience
- ASIC methodology expertise
- Microarchitecture design
- RTL quality checks (Lint, CDC)
- SystemVerilog coding
- Master's/PhD in EE/CS
- 6+ years IP design experience
- Low power estimation, timing closure, synthesis
- Python/Perl scripting
- UPF checks
5 skills required
Job Details
Minimum qualifications:
- Bachelor’s degree in Electrical or Computer Engineering or equivalent practical experience.
- 5 years of experience with Register-Transfer Level (RTL) design using Verilog/System Verilog and microarchitecture.
- 5 years of experience with ARM-based System on a Chip (SoCs), interconnects and Application-Specific Integrated Circuit (ASIC) methodology.
- Experience with a coding language like Python or Perl.
Preferred qualifications:
- Master's degree or PhD in Electrical Engineering, Computer Science, or equivalent practical experience.
- 6 years of industry experience with Intellectual Property (IP) design.
- Experience with methodologies for Register-Transfer Level (RTL) quality checks (e.g., Lint, CDC, RDC).
- Experience with methodologies for low power estimation, timing closure, synthesis.
About the job
In this role, you will design foundation and chassis IPs (e.g., Network on
Chip (NoC), Clock, Debug, IPC, Memory Management Unit (MMU) and other peripherals) for Pixel System on a Chip (SoCs). You will collaborate with members of architecture, software, verification, power, timing, synthesis, etc. to specify and deliver a quality Register-Transfer Level (RTL). You will solve technical problems with micro-architecture, low power design methodology and evaluate design options with performance, power and area in mind.
Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.
Responsibilities
- Work as part of the team that delivers coherent fabric interconnect solutions.
- Define microarchitecture details such as interface protocol, block diagram, data flow, pipelines, etc.
- Perform RTL development (SystemVerilog), debug functional/performance simulations.
- Perform RTL quality checks including Lint, CDC, Synthesis, UPF checks.
- Participate in synthesis, timing/power estimation, and FPGA/silicon bring-up.
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