Design and Verification Silicon Manager

1 Day ago • 8 Years + • Research & Development

Job Summary

Job Description

This role involves leading and managing verification activities for complex Slow-Slow (SS) or SoC within Google. Responsibilities include developing verification infrastructure and methodology for complex mobile SoC IP or SS blocks, collaborating with design teams to integrate verification methodology, optimizing and improving methodologies for efficiency, and collaborating with internal/external CAD teams to develop new verification solutions. The ideal candidate will have extensive experience in Design Verification, UVM, System Verilog, PSS, formal or emulation based SimXL methodologies, and ideally experience with Operating Systems, Memory Management, and various hardware interfaces. The position requires leadership skills, collaboration abilities, and a commitment to improving the quality and efficiency of verification processes.
Must have:
  • 8+ years in Design Verification
  • UVM, System Verilog expertise
  • Experience with PSS, formal/emulation
  • Lead verification activities for complex SoC/SS
  • Develop verification infrastructure and methodology
Good to have:
  • Master's/PhD in EE or CS
  • Experience with OS, Memory Mgmt, Caches
  • Formal verification, SVA, assertion-based verification
  • Experience spanning simulation, emulation, FPGA prototypes
  • Hardware/Software interfacing experience

Job Details

Minimum qualifications:

  • Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
  • 8 years of experience in Design Verification.
  • Experience constructing reusable verification components and environments using UVM, System Verilog or equivalent.
  • Experience in Portable Stimulus Standard (PSS), formal or emulation based SimXL methodologies.

Preferred qualifications:

  • Master's degree or PhD in Electrical Engineering or Computer Science, or a related field.
  • Experience in one or more of the following: Operating Systems, Memory Management, Caches Hierarchies, Coherency, Memory Consistency Models, Memory Ordering, DDR/LPDDR, PCIe, or Packet Processors.
  • Experience working with software teams to define hardware/software interfacing including control/status registers, security, and error handling.
  • Experience with Formal verification techniques, System Verilog Assertions (SVA) and assertion-based verification.
  • Experience building verification methodologies that span simulation, emulation and FPGA prototypes.

About the job

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.

Responsibilities

  • Lead and manage verification activities for complex Slow-Slow (SS) or SoC.
  • Develop all aspects of logic verification infrastructure and methodology for complex mobile SoC IP or SS blocks.
  • Collaborate with design teams to ensure integration of verification methodology into the design process.
  • Optimize and improve verification methodologies to increase efficiency and effectiveness.
  • Collaborate with both external and internal CAD teams to develop new verification solutions that can improve the quality and efficiency.

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