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Full Chip CAD Physical Design Verification Engineer

Tel Aviv District, Israel (On-site)

Full Chip CAD Physical Design Verification Engineer

3 Days ago • All levels • Research & Development

About the job

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python

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Job Description

This Full Chip CAD Physical Design Verification Engineer role at Google involves contributing to the development of custom silicon solutions for Google's direct-to-consumer products. Responsibilities include demonstrating understanding of the RTL-to-GDSII flow using Cadence and Synopsys tools, implementing complex SoCs and subsystems, and expertise in floorplanning, power grid design, and place-and-route methodologies. Advanced node design (5nm and below) knowledge and scripting skills (TCL, Python) are essential. The role requires contributing to innovation in hardware, delivering high performance, efficiency, and integration. The team is part of Google's Technical Infrastructure, ensuring the smooth operation of Google's products and services worldwide.

Must have:

RTL-to-GDSII flow understanding
Cadence & Synopsys tool experience
Floorplanning, power grid design, place-and-route
Advanced node design (5nm+)
TCL & Python scripting skills

Good to have:

Master's degree in Computer/Electronics Engineering
Experience in silicon quality or reliability

Minimum qualifications:

Bachelor's degree in Electrical Engineering, Computer Science, or a related field, or equivalent practical experience.
Experience in Electronic Design Automation (EDA) tools and RTL2GDS flows.
Experience in the semiconductor/EDA industry.

Preferred qualifications:

Master’s degree in Computer Engineering/Electronics Engineering.
Experience related to silicon quality or reliability.

About the job

Be part of a diverse team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.

Responsibilities

Demonstrate an understanding of the Register-Transfer Level (RTL)-to-Graphic Data Stream (GDS)II flow, with experience in using Cadence design tools.
Involve in implementing large, complex system-on-chips (SoCs), subsystems, and sub-wrappers, demonstrate an understanding of associated issues and solutions.
Possess floorplanning, power grid design, and place-and-route methodologies, with expertise in using Synopsis tools like Floorplan Compiler (FC) and formality.
Exhibit an understanding of advanced node design (e.g., 5nm and below) and related optimization techniques.
Possess scripting skills in Synopsis TCL, with expertise in Python.

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About The Company

Google

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A problem isn't truly solved until it's solved for all. Googlers build products that help create opportunities for everyone, whether down the street or across the globe. Bring your insight, imagination and a healthy disregard for the impossible. Bring everything that makes you unique. Together, we can build for everyone.