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RTL Design and Verification Lead, Silicon

Karnataka, India (On-site)

RTL Design and Verification Lead, Silicon

1 Hour ago • 18 Years + • Research & Development

About the job

2 skills required for this role

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front-end

innovation

Job Description

This role involves leading a team of engineers in the design, verification, and integration of multimedia, security, or AI accelerator designs into SoCs. Responsibilities include developing IP front-end designs, focusing on microarchitecture and RTL design for next-generation CPUs. The role requires proposing performance-enhancing microarchitecture features, collaborating with software and architecture teams, and delivering designs that meet PPA goals. Leading the verification team to ensure high-quality designs and working with physical design and power teams to meet frequency, power, and area targets are also crucial aspects of this position. The ideal candidate will have extensive experience in digital logic design, RTL design concepts, verification methodologies (UVM, SystemVerilog), and IP development for SoCs.

Must have:

18+ years experience in digital logic design
RTL design and verification expertise (UVM, SystemVerilog)
Experience leading design/verification teams in SoC IP development
Power, Performance, Area (PPA) optimization experience
Lead and manage engineering teams

Good to have:

Master's degree in relevant field
10+ years in people management
Experience with multimedia, security, or AI accelerator design
ASIC development lifecycle knowledge
Experience in managing architecture specifications

Minimum qualifications:

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or equivalent practical experience.
18 years of experience with digital logic design principles, RTL design concepts or verification methodologies and languages such as Universal Verification Methodology (UVM) and SystemVerilog.
Experience in leading design development or functional verification team in Intellectual Property (IP) development for SoCs including Power, Performance and Area characterizations and optimizations.

Preferred qualifications:

Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or equivalent practical experience.
10 years of experience in people management.
Experience in leading Silicon solutions development in multimedia or security or other complex SoC integrated IPs.
Experience in managing architecture specification to define Micro-architecture and its RTL implementation and verification through constrained random testbenches.
Knowledge of ASIC development life-cycle: architectural specification, vendor engagement, packaging, post-silicon validation, and system integration.

About the job

Be part of a diverse team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.Google's mission is to organize the world's information and make it universally accessible and useful. Our Devices & Services team combines the best of Google AI, Software, and Hardware to create radically helpful experiences for users. We research, design, and develop new technologies and hardware to make our user's interaction with computing faster, seamless, and more powerful. Whether finding new ways to capture and sense the world around us, advancing form factors, or improving interaction methods, the Devices & Services team is making people's lives better through technology.

Responsibilities

Lead and manage a team of engineers working on multimedia, security or AI accelerator design, verification and integration into SoC.
Develop IP front-end designs, emphasizing on microarchitecture and Register-Transfer Level (RTL) design for the next generation CPU.
Propose performance enhancing microarchitecture features, and work with software, architect and performance teams for trade-off studies. Communicate the pros and cons of microarchitecture enhancements.
Deliver designs meeting Power Performance Area (PPA) goals with production quality. Stay informed with modern techniques, interpret the techniques into design constructs, and languages in order to provide guidance to and participate in the performance evaluation effort.
Lead Verification team to ensure production of quality designs. Work with physical design and power teams to meet frequency, power, and area goals.

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About The Company

Google

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A problem isn't truly solved until it's solved for all. Googlers build products that help create opportunities for everyone, whether down the street or across the globe. Bring your insight, imagination and a healthy disregard for the impossible. Bring everything that makes you unique. Together, we can build for everyone.