Senior Design Engineer, Networking, Google Cloud

1 Month ago • 8 Years + • Network Engineering

Job Summary

Job Description

This Senior Design Engineer role at Google focuses on developing custom silicon solutions for Google's direct-to-consumer products. The team develops Application-Specific Integrated Circuits (ASICs) to accelerate data center networking. Responsibilities include project definition, design, and implementation; participation in design, architecture, and implementation of next-generation data center accelerators; performance analysis of end-to-end networking stacks using RDMA-based transports; evaluation of future ASIC designs and architecture; collaboration on new layer protocols for data center networking; defining performance hardware/software interfaces; writing micro-architecture and design specifications; and defining efficient micro-architecture and block partitioning/interfaces and flows. The role requires deep expertise in networking ASIC design, RDMA, packet processing, and high-throughput, low-latency system design.
Must have:
  • 8+ years ASIC architecture experience
  • RTL development for ASIC subsystems
  • Experience with RDMA and packet processing
  • Cross-functional experience (micro-architecture, design, verification)
  • Low latency, high throughput design experience
Good to have:
  • TCP/IP/Ethernet/PCIe/DRAM/NoC experience
  • Software team collaboration experience
  • Experience with networking switches/endpoints
  • C++, Python, or Go experience
  • Performance analysis, modeling, and simulation skills

Job Details


Minimum qualifications:

  • Bachelor's degree or equivalent practical experience.
  • 8 years of experience architecting networking ASICs from specification to production.
  • Experience working with design networking like: RDMA and or packet processing and system design principles for low latency, high throughput, security, and reliability.
  • Experience developing RTL for ASIC subsystems.
  • Experience in Cross-functional, micro-architecture, design, verification, logic synthesis, and timing closure.

Preferred qualifications:

  • Experience in Transmission Control Protocol (TCP), IP, Ethernet, PCIE and Dynamic random-access memory (DRAM), Network on Chip (NoC) principles and protocols.
  • Experience working with software teams optimizing the hardware/software interface.
  • Experience architecting networking switches, end points, and hardware offloads.
  • Experience in a procedural programming language (e.g. C++, Python, Go.).
  • Experience in estimating performance by analysis, modeling, and network simulation. Skilled in defining and driving performance test plans.
  • Understanding of packet classification, processing, queueing, scheduling, switching, routing, traffic conditioning, and telemetry.

About the job

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

In this role, you will be part of a team developing Application-Specific Integrated Circuit (ASIC) used to accelerate networking in data centers. You will have dynamic, multi-faceted responsibilities in areas such as project definition, design, and implementation. You will participate in the design, architecture, documentation, and implementation of the next generation of data center accelerators. You will be responsible for performance analysis for an end to end networking stack using your deep knowledge of RDMA based transports.

The ML, Systems, & Cloud AI (MSCA) organization at Google designs, implements, and manages the hardware, software, machine learning, and systems infrastructure for all Google services (Search, YouTube, etc.) and Google Cloud. Our end users are Googlers, Cloud customers and the billions of people who use Google services around the world.

We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including Google Cloud’s Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers.

Responsibilities

  • Participate in evaluation of future ASIC designs and general architecture for executing Google’s data center networking roadmap, off-the-shelf components, vendor co-developments, custom designs, and chiplets.
  • Collaborate in developing new layer protocols for data center networking.
  • Understand how everything interacts with software and other ASIC subsystems to implement groundbreaking data center networks.
  • Define performance hardware/software interfaces. Write micro-architecture and design specifications.
  • Define efficient micro-architecture and block partitioning/interfaces and flows.

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