Senior Multimedia Design Verification Engineer, Silicon

Minimum qualifications:

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
  
• Experience in verifying digital systems using standard IP components/interconnects (microprocessor cores, hierarchical memory subsystems).
• Experience in verifying digital logic at Register Transfer Level(RTL) using SystemVerilog for Application-Specific Integrated Circuit(ASICs).
  
• Experience with object oriented programming.

Preferred qualifications:

• Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture, or equivalent practical experience.
• Experience with Camera Image Signal Processor(ISP) image processing or other multimedia IPs such as Display or Video Codec.
  
• Experience with verification techniques, System Verilog Assertions (SVA) and assertion-based verification.
• Experience with Gate-Level Simulation(GLS), low-power Design Verification(DV), and support of System-on-Chip(SOC) DV.
  
• Experience creating and using verification components and environments in a standard verification methodology such as UVM.