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Senior Network Design Engineer, Google Cloud

Senior Network Design Engineer, Google Cloud

1 Month ago • 8 Years + • Network Engineering • Undisclosed

About the job

5 skills required for this role

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cpp

python

innovation

networking

cross-functional

Job Description

Google is seeking a Senior Network Design Engineer to contribute to the development of custom silicon solutions for its direct-to-consumer products. This role involves designing and implementing ASICs to accelerate data center networking. Responsibilities include participating in ASIC design evaluation, developing new layer protocols, understanding hardware/software interactions, defining performance interfaces, and writing micro-architecture and design specifications. The engineer will be responsible for performance analysis of the end-to-end networking stack, focusing on RDMA-based transports. The role requires deep expertise in networking ASICs, RDMA, packet processing, and low-latency, high-throughput system design. The ideal candidate will possess experience in RTL development, micro-architecture, verification, and timing closure.

Must have:

8+ years architecting networking ASICs
RDMA and packet processing experience
RTL development for ASIC subsystems
Cross-functional experience (design, verification, synthesis)
Performance analysis and testing

Good to have:

TCP/IP, Ethernet, PCIe, DRAM, NoC knowledge
Network simulation and modeling skills
Hardware/software interface optimization
Experience with networking switches and endpoints
C++, Python, or Go programming skills
Understanding of packet classification, processing, queueing, scheduling, switching, routing, traffic conditioning, and telemetry

Minimum qualifications:

Bachelor's degree or equivalent practical experience.
8 years of experience architecting networking ASICs from specification to production.
Experience working with design networking like: RDMA and or packet processing and system design principles for low latency, high throughput, security, and reliability.
Experience developing RTL for ASIC subsystems.
Experience in Cross-functional, micro-architecture, design, verification, logic synthesis, and timing closure.

Preferred qualifications:

Experience in Transmission Control Protocol (TCP), IP, Ethernet, PCIE and Dynamic random-access memory (DRAM), Network on Chip (NoC) principles and protocols.
Experience in estimating performance by analysis, modeling, and network simulation. Skilled in defining and driving performance test plans.
Experience working with software teams optimizing the hardware/software interface.
Experience architecting networking switches, end points, and hardware offloads.
Experience in a procedural programming language (e.g. C++, Python, Go.).
Understanding of packet classification, processing, queueing, scheduling, switching, routing, traffic conditioning, and telemetry.

About the job

Be part of a diverse team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

In this role, you will be part of a team developing Application-Specific Integrated Circuit (ASIC) used to accelerate networking in data centers. You will have dynamic, multi-faceted responsibilities in areas such as project definition, design, and implementation. You will participate in the design, architecture, documentation, and implementation of the next generation of data center accelerators. You will be responsible for performance analysis for an end to end networking stack using your deep knowledge of RDMA based transports.

Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.

Responsibilities

Participate in evaluation of future ASIC designs and general architecture for executing Google’s data center networking roadmap, off-the-shelf components, vendor co-developments, custom designs, and chiplets.
Collaborate in developing new layer protocols for data center networking.
Understand how everything interacts with software and other ASIC subsystems to implement groundbreaking data center networks.
Define performance hardware/software interfaces. Write micro-architecture and design specifications
Define efficient micro-architecture and block partitioning/interfaces and flows

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About The Company

Google

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