Senior RTL Design Engineer, Camera, Machine Learning, Silicon
Job Summary
Job Description
- 5+ years experience in digital logic design
- RTL design using Verilog/SystemVerilog
- Logic synthesis, low-power design techniques
- Scripting (Perl/Python)
- RTL verification, test planning, coverage analysis
- Master's/PhD in EE/CE/CS
- Camera ISP, ML IP, or multimedia IP experience
- ASIC design methodologies (clock/reset checks)
- Bonus
- Equity
- Benefits
5 skills required
Job Details
Minimum qualifications:
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
- 5 years of experience with digital logic design principles, RTL design concepts, and languages such as Verilog or SystemVerilog.
- Experience with logic synthesis techniques to optimize RTL code, performance and power as well as low-power design techniques.
- Experience with a scripting language such as Perl or Python.
Preferred qualifications:
- Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
- Experience implementing Camera ISP image processing blocks, Machine Learning (ML) IPs, or other multimedia IPs such as Display or Video Codecs.
- Experience with Application-Specific Integrated Circuit (ASIC) design methodologies for clock domain checks and reset checks.
About the job
Be part of a diverse team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
In this role, you will be responsible for Register-Transfer Level (RTL) design development of camera and machine learning designs. This includes RTL coding, lint cleanup, System on a Chip (SoC) IP release flows, architecture, micro-architecture, power, performance and area (PPA) optimizations, test planning collaboration, and coverage reviews and closure for high quality and optimized Core IP deliveries.
Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.
The US base salary range for this full-time position is $156,000-$229,000 + bonus + equity + benefits. Our salary ranges are determined by role, level, and location. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.
Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about .
Responsibilities
- Perform Verilog/SystemVerilog RTL coding, function/performance simulation debug, and Lint/CDC/FV/UPF checks.
- Perform RTL verification using industry standard methodologies. Participate in test planning and coverage analysis.
- Develop RTL implementations that meet engaged power, performance and area goals.
- Participate in synthesis, timing/power closure and field programmable gate array (FPGA)/silicon bring-up.
- Create tools/scripts to automate tasks and track progress.
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About The Company
A problem isn't truly solved until it's solved for all. Googlers build products that help create opportunities for everyone, whether down the street or across the globe. Bring your insight, imagination and a healthy disregard for the impossible. Bring everything that makes you unique. Together, we can build for everyone.
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