Senior SoC Power Engineer

1 Month ago • 8 Years + • Research & Development

Job Summary

Job Description

As a Senior SoC Power Engineer at Google Cloud, you'll be part of a team developing custom silicon solutions for Google's products. You will work on power-related flows across the chip development lifecycle, optimizing power consumption and efficiency. Responsibilities include developing power reduction methodologies, collaborating with architecture, frontend, and backend teams, supporting power delivery and packaging teams, defining power scenarios and tests, and ensuring power goals are met. You'll partner with hardware, software, and data center controls teams to contribute to Google Cloud's infrastructure and create CPU SoC solutions.
Must have:
  • 8+ years of experience in power modeling, delivery, and distribution network/design
  • Experience with power estimation and optimization flows and tools
  • Experience with Vector based Physical Design Power Tools (e.g., PTPX Prime power)
  • Bachelor's degree in CS, EE, or related field
Good to have:
  • Power optimization techniques (multi Vth/power/voltage domain design, clock gating, etc.)
  • Scripting languages (Python, Perl, TCL, or Bash)
  • Knowledge of software and architectural design's impact on power and thermal behavior
  • Knowledge of system software components (Linux, drivers, etc.)

Job Details


Minimum qualifications:

  • Bachelor's degree in Computer Science, Electrical Engineering, or a related technical field, or equivalent practical experience.
  • 8 years of experience with power modeling, power delivery, and power distribution network/design.
  • Experience in power estimation and optimization flows and tools.
  • Experience with Vector based Physical Design Power Tools (e.g. PTPX Prime power).

Preferred qualifications:

  • Experience with power optimization techniques (multi Vth/power/voltage domain design, clock gating, power gating, DVFS/AVS, etc.) and power management.
  • Experience with scripting languages (i.e., Python, Perl, TCL or Bash).
  • Knowledge of the impact of software and architectural design decisions on power and thermal behavior of the system (thermal mitigation and scheduling, cross-layer policy design).
  • Knowledge of system software components (i.e., Linux, drivers, runtime performance analysis, etc.).

About the job

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

As a System on a Chip (SoC) Power Engineer in Google Cloud, you will be part of the server chip design team. Power related flows across the chip development end to end.

You will have the opportunity to impact the Google Cloud Infrastructure, combine the latest innovations in algorithms and integrate circuits to create CPU SoC solutions for Google Cloud. You will partner with hardware, software, and data center controls teams to provide silicon and technology roadmaps.

The ML, Systems, & Cloud AI (MSCA) organization at Google designs, implements, and manages the hardware, software, machine learning, and systems infrastructure for all Google services (Search, YouTube, etc.) and Google Cloud. Our end users are Googlers, Cloud customers and the billions of people who use Google services around the world.

We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including Google Cloud’s Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers.

Responsibilities

  • Develop methodology of SoC roll up of power reduction, projection, configuration, test plan and tools.
  • Work intact with Architecture, Frontend and Backend teams driving power reduction features (both logic and circuit).
  • Support power delivery and packaging teams with simulations and scenario definitions.
  • Work intact with Architecture and DV to define power scenarios and tests, debug, and integrate into the flow.
  • Track power goals are met throughout execution.

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