This role involves designing and integrating custom silicon solutions for Google's products. Responsibilities include owning microarchitecture, implementation, and integration of SoC Chassis and subsystems; performing quality checks (Lint, CDC, RDC, VCLP); driving design methodology and code reviews; and identifying improvements for power, performance, and area. The ideal candidate will have 3+ years of experience in ASIC development with Verilog/SystemVerilog, VHDL, or Chisel, experience in ASIC design verification, synthesis, timing/power analysis, and DFT, and experience in SoC integration domains (clocking, debug, fabrics, security, or low power methodologies). The position is based in Bengaluru, India and is part of Google's effort to build the next generation of hardware.