Backend Physical Design Engineer

2 Months ago • 3-5 Years • Research & Development

About the job

Job Description

Seeking a Backend Physical Design Engineer with 3+ years of experience in layout activities, floor-planning, partitioning, placement, clock tree synthesis, route and physical verification. Proficient in EDA tools across floorplan/partition/placement/CTS/route stages for SoC TOP. Experience with backend EDA tools like Genus/Innovus/Quantus/Tempus, DC/Star-RCXT/PT, PrimeRail/Voltus, Redhawk is required.
Must have:
  • Backend Physical Design
  • EDA Tools Proficiency
  • Floorplan/Partition/Placement
  • Clock Tree Synthesis
Good to have:
  • Timing Constraints
  • Physical Constraints
  • Tcl and Perl
  • Automation Savvy
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About the job

Job Description:

In this role, the Engineer will apply and lead Broadcom's proven design methodology and milestone flow to meet Broadcom's rigorous criteria for achieving Right-first time silicon.

Candidate should have very good experience in layout activities of block and SoC level. Should be well experienced in floor-planning, partitioning, placement, clock tree synthesis, route and physical verification.

Responsibilities include, but not limited to:


  • Understanding of SoC for top-down/bottom-up physical design integration in 7nm and lower technologies
  • Drive Sub-block/partition decisions, floorplan for the best PPAS
  • Must have deep functional knowledge of P&R flows, should be able to catch up quickly on internal flows, adapt.
  • Implement timing and functional ECO
  • P&R, Extraction, Physical verification, work towards STA closure
  • Build automation flows wherever needed/adapt to existing flows for re-use
  • Must be proficient in any of the Cadence/Synospys/Mentor EDA tools for P&R, PV, STA, ECO
  • Needs to be automation savvy with high expertise in one of the programming languages used in the industry
  • Clearly know requisites for executing his/her job and lead by example
  • Bring tangible improvement in TAT with better quality


Minimum Qualifications:


  • MSEE/MSCS 3+ years (BSEE/BSCS 5+ years)
  • A deep understanding of backend digital design flow
  • Proficient in timing constraints, physical constraints
  • Proficient in handling EDA tools across floorplan/partition/placement/cts/route stages for SoC TOP.
  • Proficient with backend EDA tools viz, Genus/Innovus/Quantus/Tempus, DC/Star-RCXT/PT, PrimeRail/Voltus, Redhawk
  • Proficiency in Tcl and Perl
  • Excellent analytical skills
  • Shown ability to collaborate in a multi-functional environment, cross-site or cross-time zone


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About The Company

A global infrastructure technology leader built on more than 60 years of innovation, collaboration and engineering excellence.

 

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Singapore, Singapore (On-Site)

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