Senior ASIC Physical Design Engineer

1 Month ago • 3 Years + • Research & Development

Job Summary

Job Description

NVIDIA's ASIC-PD team seeks a Senior ASIC Physical Design Engineer to contribute to the physical design process, from RTL to GSDII. Responsibilities include design quality checks, synthesis, formal verification, partitioning, constraint development, timing analysis and closure, and flow automation. The role involves collaboration with various teams (ASIC/P&R/DFT/SI/ARCH) to optimize designs for advanced process technologies and large-scale chip development. The successful candidate will handle STA for hierarchical designs, constraint creation, timing budget management, and implementation of chip partitions and floorplans. Experience with Synopsys and Cadence EDA tools is essential.
Must have:
  • 3+ years experience in IC design implementation
  • Proficiency in Synopsys (DC/PT/Formality) and Cadence (LEC)
  • STA, timing closure, constraint creation
  • Synthesis, netlist QC, formal verification
  • Chip partitioning, floorplanning
Good to have:
  • Proficient in Perl, Python, or TCL
  • Excellent English communication skills
  • MSEE degree

Job Details

Job Description

ASIC-PD team is hiring both junior and senior engineers, whose work scope is physical design from RTL to GSDII: design quality check, synthesis, formal check, partitioning, constraint (for both design and process), async check, timing analysis/fixing/signoff, also all related flow. Join us, you will work together with expertise in all these areas; you will not only work for physical application, but also drive physical friendly design with all related teams: ASIC/P&R/DFT/SI/ARCH etc.; you will work for the most advanced process/technology, the biggest chip in the world.

What you’ll be doing:

  • STA for hierarchical design.

  • Constraints creation and validation, timing budget.

  • Timing closure for both partition and full chip level.

  • Special timing closure, such as io, test, clock etc.

  • Synthesis, Netlist quality check, Formal Verification.

  • Implement chip partition and floorplan.

  • Function eco creation.

  • Develop and enhance entire timing closure flow from frontend (pre-layout) to backend (post-layout).

  • Flow automation development, Methodology in any of above areas.

What we need to see:

  • BSEE, (MSEE is preferred) with 3+ years or equivalent experience.

  • Project experience in IC design implementation.

  • Courses taken in circuit design, digital design.

  • Hand-on experience in EDA software from Synopsys (DC/PT/Formality), Cadence (LEC) is preferred.

Ways to stand out from the crowd:

  •  Proficient user of Perl, Python or TCL is preferred.

  •  Excellent English communication skill.

NVIDIA is widely considered to be one of the technology world’s most desirable employers. We have some of the most brilliant and talented people on the planet working for us. If you're creative and autonomous, we want to hear from you!

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Since its founding in 1993, NVIDIA (NASDAQ: NVDA) has been a pioneer in accelerated computing. The company’s invention of the GPU in 1999 sparked the growth of the PC gaming market, redefined computer graphics, ignited the era of modern AI and is fueling the creation of the metaverse. NVIDIA is now a full-stack computing company with data-center-scale offerings that are reshaping industry.


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