Lead Engineer - RTL Design

Why this position matters:
As a Design Verification Engineer in the R&D Digital team at Silicon Labs, Hyderabad, you will play a key role in designing & verifying digital blocks, verifying operation and performance. Learn more about the IoT products you will be working with here.

• You are responsible for the research and development of digital architectures and IPs from concept to production. We develop compute engines (AI,ML), processors (RISC-V), accelerators, peripherals and system IP. Our activities include advanced research & development, high-level modeling, architecture, RTL design, timing, power and area optimization, formal and UVM verification within an automated framework. We value innovation, simplicity, quality, and smart development processes within a highly collaborative and learning-driven team.
• You will also work on exciting and market leading highly integrated SoCs for various Internet of Things markets. Our award-winning technologies provide our customers a full solution: advanced security, world class energy efficiency, simplicity, powerful operating systems, & options that are cost effective.
• You will focus on specification, RTL Design, Verification, FPGA emulation of digital blocks and chip-level designs.

Silicon Labs has a track record of multiple industry firsts and of transforming and disrupting large and diversified markets. Our Design Engineers are at the forefront of that success!

Excited? See what it’s like to be a part of the Silicon Labs team

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Experience Level:

7-10 years

Education Requirements:

B.Tech/M.Tech in ECE, EEE

What skills you will need:

• Strong foundational knowledge of digital circuit design concepts, simulation, and verification techniques
• Competence in RTL coding & VLSI 

Any skills or experience in the follow areas will be considered a plus:

• Microprocessor architecture and implementation
• Low-power digital circuit design techniques
• High-speed, high-performance digital circuit design techniques
• Logic synthesis, placement, clock tree synthesis, and timing analysis
• Competence in behavioral modeling (e.g. Verilog, VerilogAMS, SystemVerilog), high-level languages (e.g., C, C++, Matlab) and scripting languages (e.g Python)
• Wired and wireless digital communications systems, DSP