Physical Design and Timing Signoff Methodology, Silicon

This role involves driving physical design and sign-off timing methodologies for mobile System on a Chips (SoCs) to enhance power, performance, and area (PPA) and yield. Responsibilities include analyzing power-performance-area trade-offs across methodologies and technologies, collaborating with cross-functional teams (architecture, IPs, design, foundry, CAD, and sign-off methodology), and ensuring optimal timing signoff conditions. The ideal candidate will have experience in timing analysis, physical design, scripting languages (Perl, Tcl, Python), physical design tool automation, and data analysis. A deep understanding of parasitic extraction tools and flows is also essential. The work contributes to developing custom silicon solutions for Google's direct-to-consumer products.