Physical Design Engineer

3 Weeks ago • 4-4 Years
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About the job

SummaryBy Outscal

We are looking for Physical Design Engineers with 4+ years of experience in SoC Synthesis, STA, PNR, and IR. Expertise in Cadence tools, Tcl scripting, and Low Power implementation is essential.

About the job

Experience: 4+ Years

Education: B.Tech/B.E/M.Tech/ME

Job Location: Bangalore, India

We are looking for 10 Physical Design Engineers with skills as below:


Description : Synthesis

  • Should be able to handle synthesis of SoC, tweak the flow to meet PPA targets
  • Should be able to debug and resolve RTL2N LEC, N2N, LP-LEC issues
  • Should be able to run CLP and resolve gate level CLP violations
  • Familiarity with Multi-voltage, multi-power domain based Low power implementation
  • Tools/Flows: Cadence: Genus, LEC, CLP
  • Makefile based flow
  • Tcl based automation


Description : STA

  • Expected to handle constraints bring-up for Func/DFT modes
  • Should have good constraints debugging skills
  • Should be familiar with timing closure at various stages (preLayout, postLayout)
  • Familiarity with Multi-voltage, multi-power domain based STA
  • Tools/Flows: Cadence: Tempus
  • Tcl based automation
  • Makefile based flow


Description : PNR/PV

  • Should be familiar with custom placement/routing using semi-automatic/manual method
  • Should have worked on Physical Verification checks for Low Power SoC (DRC, ERC, LVS, ANT, ESD, DFM)
  • Tools/Flows: Cadence: Innovus, Calibre
  • Makefile based flow
  • Tcl based automation


Description : PNR

  • Should be able to handle P&R of SoC Blocks/Top
  • Should be able to customize the PNR flow to meet PPA and low power requirements
  • Should be able to resolve timing/congestion issues
  • Should have worked on Multi-voltage, multi-power domain based designs
  • Tools/Flows: Cadence: Innovus, Calibre, Tempus
  • Makefile based flow
  • Tcl based automation


Description : PNR/IR

  • Should be able to handle power grid development using tool automation and custom scripts
  • Should have handled SoC level EM/IR analysis (Static, Dynamic IR, power/signal EM) for SoC with power switches
  • Should be able to analyse, root-cause and fix IRdrop issues
  • Tools/Flows Cadence: Innovus, Redhawk-SC
  • Makefile based flow
  • Tcl based automation



Working time: Monday - Friday

Contact: Ms. Van Anh – WhatsApp: +84 935059669

Email: anh.thivannguyen@ust.com

About The Company

UST is a global digital transformation solutions provider. For more than 20 years, UST has worked side by side with the world’s best companies to make a real impact through transformation. Powered by technology, inspired by people and led by purpose, UST partners with their clients from design to operation. With deep domain expertise and a future-proof philosophy, UST embeds innovation and agility into their clients’ organizations. With over 30,000 employees in 30 countries, UST builds for boundless impact—touching billions of lives in the process.

Karnataka, India (On-Site)

Karnataka, India (On-Site)

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Karnataka, India (On-Site)

Karnataka, India (On-Site)

Karnataka, India (On-Site)

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