Senior Memory Management Unit Architect, Silicon

1 Month ago • 5 Years + • Research & Development

Job Summary

Job Description

This Senior Memory Management Unit Architect role at Google involves collaborating with hardware and software architects to define IOMMU architecture and topology for current and next-generation products. Responsibilities include interfacing with security architects, coordinating with modeling and performance teams, working with hardware design and verification teams, and exploring OS and hypervisor support for memory and device virtualization. The ideal candidate will have extensive experience in architecture/microarchitecture related to IOMMUs, caches, coherent interconnects, and memory systems, along with experience in ARM architecture and Android/Linux virtual memory management. The role contributes to the development of technologies for the SOC Platform IP and involves patent filing.

Must have:

5+ years experience in IOMMUs, caches, memory systems
ARM architecture, TrustZone, memory model expertise
Android/Linux virtual memory management knowledge
Collaboration with hardware/software architects
IOMMU architecture definition and topology design

Good to have:

Master's or PhD in relevant field
Experience with simulation tools (SystemC/TLM, C++, Python)
SoC pre/post-silicon performance analysis
System Verilog/Verilog knowledge

4 skills required

4 skills required for this role

Add these skills to join the top 1% applicants for this job

python

linux

innovation

performance-analysis

Job Details

Minimum qualifications:

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
5 years of experience in architecture/microarchitecture/modeling/performance/design in one or more of these areas: IOMMUs, Caches, Coherent interconnects, Memory Systems.
Experience in Advanced RISC Machine (ARM) architecture, ARM TrustZone Security Architecture, ARM memory model and Android/Linux Virtual Memory Management.

Preferred qualifications:

Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
Experience working with simulation tools (System C/TLM, C++, Python).
Experience in SoC system pre-silicon or post-silicon performance analysis and tuning.
Knowledge with designing/implementing/validating in two or more of these areas: IOMMUs, Caches, Coherent interconnects, Memory Systems.
Knowledge of Hardware Description Language languages such as System Verilog, Verilog.

About the job

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

As part of the Google Silicon Platform IP team, you will collaborate with hardware and software architects to define interconnect architectures focused on Google Tensor SoC and other associated products. Your primary focus will be on our next-generation IOMMU (Input-Output Memory Management Unit) architecture, topology, microarchitecture and performance. As part of this team, you will participate in the development of technologies for the SOC Platform IP and filing associated patents.

Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.

Responsibilities

Collaborate with hardware and software architects to define IOMMU architecture and topology for ongoing products and next-generation IOMMUs.
Interface with security and access-control architects to refine and improve the architecture.
Coordinate with modeling and performance teams to develop C-models, simulate and analyze performance, power, area tradeoffs.
Work with hardware design, verification, emulation and validation teams to build, test and refine the hardware architecture.
Explore and evaluate support for operating systems, hypervisors, memory and device virtualization.