Full Chip STA Engineer

3 Months ago • 3 Years + • Research & Development

Job Summary

Job Description

NVIDIA seeks a Full Chip STA Engineer to join their Networking Silicon team. Responsibilities include full chip level STA convergence from early stages to signoff, participating in floor plan design and netlist creation for timing optimization, defining and optimizing STA signoff flows and methodologies with CAD, integrating digital partitions and analog IPs, working with logic design and DFT engineers to define and implement constraints, and optimizing them for runtime and efficiency. The ideal candidate possesses a B.Sc./M.Sc. in Electrical Engineering/Computer Engineering, 3+ years of experience in physical design and STA, proven experience in RTL2GDS and STA flows, and familiarity with EDA tools like Synopsys and Cadence.
Must have:
  • Full Chip STA Convergence
  • Floor plan design & Netlist creation
  • STA signoff flows & methodologies
  • Digital & Analog IP integration
  • Constraint definition & implementation
  • 3+ years experience in physical design and STA
  • RTL2GDS and STA flows knowledge
  • Familiarity with Synopsys & Cadence

Job Details

NVIDIA is looking for a best-in-class STA Engineer to join our outstanding Networking Silicon engineering team, developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency! Come and take a part in designing our groundbreaking large scale and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a significant impact in a technology-focused company.

What you will be doing:

  • Be in charge of full chip level STA convergence from early stages to signoff.

  • Take part in Full Chip floor plan design and Netlist creation with aim to optimize timing convergence and work efficiency.

  • Define and optimize, together with CAD, STA signoff flows and methodologies.

  • Digital Partitions' and analog IPs' timing integration, giving feedback and driving convergence.

  • Work closely with logic design and DFT engineers to define and implement constraints for the various work modes, including optimizing them for runtime and efficiency.

What we need to see:

  • B.SC./ M.SC. in Electrical Engineering/Computer Engineering.

  • 3+ years of experience in physical design and STA

  • Proven experience in RTL2GDS and STA flows and methodologies.

  • Familiarity with physical design EDA tools (such as Synopsys, Cadence, etc.) and timing signoff (Primetime).

  • Great teammate.

NVIDIA has some of the most forward-thinking people in the world working for us. Are you a creative and autonomous engineer who loves a challenge? Are you ready to become the engineer you always wanted to be? Come and be part of the best physical design team in the industry!

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About The Company

Since its founding in 1993, NVIDIA (NASDAQ: NVDA) has been a pioneer in accelerated computing. The company’s invention of the GPU in 1999 sparked the growth of the PC gaming market, redefined computer graphics, ignited the era of modern AI and is fueling the creation of the metaverse. NVIDIA is now a full-stack computing company with data-center-scale offerings that are reshaping industry.

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