Principal Logic Engineer

Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the team behind Microsoft’s expanding Cloud Infrastructure and responsible for powering Microsoft’s “Intelligent Cloud” mission. SCHIE delivers the core infrastructure and foundational technologies for Microsoft's over 200 online businesses including Bing, MSN, Office 365, Xbox Live, Teams, OneDrive, and the Microsoft Azure platform globally with our server and data center infrastructure, security and compliance, operations, globalization, and manageability solutions. Our focus is on smart growth, high efficiency, and delivering a trusted experience to customers and partners worldwide and we are looking for a Principal Logic Engineer to help achieve that mission.

As Microsoft's cloud business continues to grow, the ability to deploy new offerings and hardware infrastructure on time in high volume with high quality and lowest cost is of paramount importance. To achieve this goal, the Cloud Compute Development Organization (CCDO) team is instrumental in defining and delivering operational measures of success for hardware manufacturing, improving the planning process, quality, delivery, scale and sustainability related to Microsoft cloud hardware. We are looking for a Principal Logic Engineer for customer focused solutions, insight and industry knowledge to envision and implement future technical solutions that will manage and optimize the Cloud infrastructure.

We are looking for a Principal Logic Engineer with experience in high performance Dynamic Random-Access Memory(DRAM) memory controllers and DDR4/5 PHYs.

Microsoft’s mission is to empower every person and every organization on the planet to achieve more. As employees we come together with a growth mindset, innovate to empower others, and collaborate to realize our shared goals. Each day we build on our values of respect, integrity, and accountability to create a culture of inclusion where everyone can thrive at work and beyond.

In alignment with our Microsoft values, we are committed to cultivating an inclusive work environment for all employees to positively impact our culture every day.

Required Qualifications:

• 9+ years of related technical engineering experience
  • OR Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 6+ years technical engineering experience or internship experience
  • OR Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 4+ years technical engineering experience or internship experience
  • OR Doctorate degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 3+ years technical engineering experience.
• 8+ years of experience with Double Data Rate 4(DDR4) or Double Data Rate 5 (DDR5) Dynamic Random-Access Memory(DRAM) Memory Controller design.
• Knowledge of Joint Electron Device Engineering Council (JEDEC) DDR5 Specification.
• Fluency in Verilog and System Verilog and Dynamic Random-Access Memory Physical Layer (DRAM PHY) and Interface Protocol(DFI) and High speed digital design experience.

Other Requirements:

• Ability to meet Microsoft, customer and/or government security screening requirements are required for this role. These requirements include but are not limited to the following specialized security screenings: Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter.

Preferred Qualifications:

• Proficient with synthesis tools.
• Proficient with scripting tools. 

Silicon Engineering IC5 - The typical base pay range for this role across the U.S. is USD $137,600 - $267,000 per year. There is a different range applicable to specific work locations, within the San Francisco Bay area and New York City metropolitan area, and the base pay range for this role in those locations is USD $180,400 - $294,000 per year.

Certain roles may be eligible for benefits and other compensation. Find additional benefits and pay information here:    

Microsoft will accept applications for the role until December 13, 2024. 

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• Microarchitect major blocks of a DRAM Memory Controller and implement the design with high quality in Verilog Register Transfer Level (RTL).
• Interface with PHY vendor.
• Work closely with front end design and physical design teams to ensure correctness of the Micro Controller(MC) design.
• Implement any additional required functional units in Verilog.
• Ensure high quality of the design from the perspectives of functionality, timing, Clock Domain Crossing (CDC), Reset Domain Crossing (RDC), Logic Equivalence Check (LEC).
• Other
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