Senior CPU Design Verification Engineer

2 Days ago • 3 Years + • Research & Development

Job Summary

Job Description

Google Cloud seeks a Senior CPU Design Verification Engineer to contribute to custom silicon solutions powering future direct-to-consumer products. Responsibilities include planning verification of digital design blocks, creating and enhancing constrained-random verification environments using SystemVerilog/UVM or Specman, identifying and writing coverage measures, debugging tests with design engineers, and leading coverage to identify verification holes. This role involves close collaboration with design and verification teams, managing the verification lifecycle, and building efficient verification environments to expose design bugs. The ideal candidate will have expertise in digital logic verification, standard IP components, and verification methodologies.
Must have:
  • 3+ years RTL verification experience (SystemVerilog, Specman)
  • Experience verifying digital systems using standard IP
  • Proficiency in standard verification methodology
  • Create and enhance constrained-random verification environments
  • Identify and write coverage measures
  • Debug tests with design engineers
Good to have:
  • Master's degree in EE or CS
  • CPU implementation experience
  • Assembly language or SoC experience
  • UVM experience
  • Scripting languages (Python, Perl, Shell, etc.)

Job Details


Minimum qualifications:

  • Bachelor's degree in Electrical Engineering or equivalent practical experience.
  • 3 years of experience verifying digital logic at RTL level using SystemVerilog, or Specman/E for FPGAs or ASICs.
  • Experience verifying digital systems using standard IP components/interconnects (microprocessor cores, hierarchical memory subsystems).
  • Experience creating and using verification components and environments in standard verification methodology.

Preferred qualifications:

  • Master’s degree in Electrical Engineering or Computer Science.
  • Experience with CPU implementation, assembly language, or compute System on a Chip (SOC).
  • Experience with UVM, SystemVerilog, or other scripting languages (e.g., Python, Perl, Shell, Bash, etc.).

About the job

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

As a Executive CPU Design Verification Engineer, you will work as part of a Research and Development team, and you will build verification components, constrained-random testing, system testing, and verification closure. As part of our server chip design team, you will verify digital designs. You will collaborate closely with design and verification engineers in projects and perform direct verification. You will build efficient and effective constrained-random verification environments that exercise designs through their corner-cases and expose all types of bugs. You will manage the full lifecycle of verification which can range from verification planning, test execution or collecting, and closing coverage.

The ML, Systems, & Cloud AI (MSCA) organization at Google designs, implements, and manages the hardware, software, machine learning, and systems infrastructure for all Google services (Search, YouTube, etc.) and Google Cloud. Our end users are Googlers, Cloud customers and the billions of people who use Google services around the world.

We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including Google Cloud’s Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers.

Responsibilities

  • Plan the verification of digital design blocks by fully understanding the design specification and interacting with design engineers to identify important verification scenarios.
  • Create and enhance constrained-random verification environments using SystemVerilog/UVM, or Specman.
  • Identify and write all types of coverage measures for stimulus and corner-cases.
  • Debug tests with design engineers to deliver functionally correct design blocks.
  • Lead coverage measures to identify verification holes and to show progress towards tape-out.

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