Physical Design CAD Engineer, Static Timing Analysis
Job Summary
Job Description
- 5+ years experience in RTL2GDS and STA
- Proficiency in physical design tools (Synopsys, Cadence)
- Experience with timing sign-off (Primetime)
- Strong understanding of high-frequency design
- STA methodology definition and implementation
- Experience with AC timing
- CDC design and constraints expertise
- ASIC physical design experience
- Knowledge of DFT modes and signal integrity
2 skills required
Job Details
Minimum qualifications:
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
- 5 years experience in RTL2GDS, Static Timing Analysis (STA) flows, and methodologies.
- Experience with physical design tools (e.g., Synopsys, Cadence) and timing signoff (Primetime).
- Experience with Static Timing Analysis, sign-off corner definitions, process margining, SDC development, high frequency convergence, and setting up frequency goals with technology scaling.
Preferred qualifications:
- Experience with Alternating Current (AC) timing from specs to implementation.
- Experience with CppDefensiveCoding (CDC) design and CDC constraints.
- Experience in Application-Specific Integrated Circuit (ASIC) physical design, physical design flows and methodologies, synthesis, place and route, and formal verification.
- Knowledge of Design for testing (DFT) modes, noise and signal integrity effects.
About the job
Our computational challenges are so big, complex and unique we can't just purchase off-the-shelf hardware, we've got to make it ourselves. Your team designs and builds the hardware, software and networking technologies that power all of Google's services. As a Hardware Engineer, you design and build the systems that are the heart of the world's largest and most powerful computing infrastructure. You develop from the lowest levels of circuit design to large system design and see those systems all the way through to high volume manufacturing. Your work has the potential to shape the machinery that goes into our cutting-edge data centers affecting millions of Google users.
The ML, Systems, & Cloud AI (MSCA) organization at Google designs, implements, and manages the hardware, software, machine learning, and systems infrastructure for all Google services (Search, YouTube, etc.) and Google Cloud. Our end users are Googlers, Cloud customers and the billions of people who use Google services around the world.
We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including Google Cloud’s Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers.
Responsibilities
- Coordinate with teams like Architecture, Logic Design, Design for testing (DFT), and Physical Design from early stages to implement constraints for the various modes through timing convergence to full signoff.
- Define overall Static Timing Analysis (STA) methodology, STA infrastructure, and sign-off convergence flows.
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