Senior Design Engineer, Coherent High Speed Interconnect

NVIDIA is looking for a Senior Design Engineer for our Coherent High Speed Interconnect team!
 

For two decades, NVIDIA has pioneered visual computing, the art and science of computer graphics. With our invention of the GPU - the engine of modern visual computing - the field has grown to encompass video games, movie production, product design, medical diagnosis, and scientific research! Today, we stand at the beginning of the next era, the AI computing era, ignited by a new computing model, GPU deep learning. This new model - where deep neural networks are trained to recognize patterns from substantial amounts of data - has shown to be deeply effective at solving the most sophisticated problems in everyday life.
 

What You'll be Doing:

• You will be working on architecture and design of our state-of-the-art high speed coherent interconnects (NVLINK-C2C) for our mobile SoCs and GPUs.

• Collaborate with architects, external partners, software engineers, and circuit designers to deliver a class leading high speed coherent interconnect.

• The NVLINK-C2C enables the creation of a new class of integrated products with NVIDIA partners, built via chiplets, allowing NVIDIA GPUs, DPUs, and CPUs to be coherently interconnected with custom silicon.

• To learn more about NVIDIA's ultra-fast chip interconnect technology visit: https://www.nvidia.com/en-us/data-center/nvlink-c2c/

• This position offers the opportunity to have real impact in a dynamic, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence. We have crafted a team of outstanding people stretching around the globe, whose mission is to push the frontiers of what is possible today and define the platform for the future of computing.

What We Need to See:

• BS or equivalent experience in Electrical Engineering or Computer Engineer or related degree required, advanced degrees (MS, PhD) a plus.

• 6+ years or relevant design experience

• Knowledge of industry standard interconnect protocols like PCIE, CXL, AXI, CHI will be useful.

• Understanding or experience with Link layer stacks including Data link layer and Physical layer

• Experience with physical layer of interconnects such as Memory (DDR, LPDDR etc..) , PCIE , SerDes

• Experience and knowledge in architecture, RTL design, performance analysis and power optimization.

• Strong working knowledge of Verilog or System Verilog.

• Good communication skills and interpersonal skills are required. A history of mentoring junior engineers and interns a huge plus.