About Marvell
Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, automotive, and carrier architectures, our innovative technology is enabling new possibilities.
At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.
Your Team, Your Impact
Marvell Central Engineering (CE) develops Marvell most advanced High-Speed SerDes (HSS) IPs covering multiple applications, Switch, Automotive, Storage, Optics, etc. Acting as the engine to the company, Central Engineering provides the source of power to every business unit in Marvell system.What You Can Expect
Responsible for understanding the logic, develop hitlist, verification environment, testcases etc., required for verifying the logic, individually
Implement verification methodologies for testbench development
Develop scripts required for running simulations and regressions and debug fails
Document the verification plan and verification documentation
Plan functional coverage/code coverage, analyze and improve coverage
Review and update verification environment and testcases
Report, track and close logic issues
Work and communicate effectively with global team
Work with designers and FW engineers to enable better verification
What We're Looking For
Bachelor’s/Master's degree in Computer Science, Electrical Engineering or related fields and 7-10 years of related professional experience. Must have good digital logic understanding and fundamentals of digital design.
Candidate must have excellent skills in digital logic verification and hardware description language (VHDL or Verilog),
Strong knowledge in object oriented programming using languages such as SystemVerilog
Must have hands on experience in hardware verification methodologies such as UVM or OVM,
Must be familiar with verification test planning and coverage driven verification closure, Verification strategies for directed and randomized testing and assertions
Must have good experience in using simulation tools and proficiency in simulation debug techniques.
Strong knowledge / experience in building the verification environment from specification and should have spec to hardware bring-up experience.
Must have hands on knowledge on test-bench development and automation, bug tracking, and regression mechanisms
Should be able to act as the team lead to determine methods and procedures on new assignments and coordinate activities of other team members to ensure successful project completion.
Experience in High Speed SerDes, clock data recovery based PHYs, Asynchronous clock domain crossing verification.
IP architecture and verification knowledge
Experience in scripting languages such as Perl
Gate level simulation and AMS simulation knowledge
Experience with Linux operating system
Experience with Cadence or any other industry tools
Should be a good team player
Good communication skills and quick learning ability.
Knowledge of standard configuration management system like CVS or SVN
Additional Compensation and Benefit Elements
With competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We’re dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what it’s like to work at Marvell, visit our Careers page.
All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.
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