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Silicon Layout Engineer

Silicon Layout Engineer

1 Month ago • 8 Years + • Research & Development

About the job

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Job Description

This Silicon Layout Engineer role at Google's Raxium group involves delivering high-performance analog layout designs for advanced process nodes (22nm and below). Responsibilities include collaborating with circuit designers, optimizing layouts for area, performance, and power, and performing verification checks (LVS, DRC). You'll contribute to layout methodologies and best practices. The ideal candidate possesses 8+ years of experience with analog circuit design and layout using tools like Cadence Virtuoso and Mentor Graphics Calibre. Experience with advanced process nodes and scripting languages is highly valued.

Must have:

8+ years analog circuit design & layout experience
Proficiency in Cadence Virtuoso & Mentor Graphics Calibre
Advanced process node (22nm and below) experience
LVS and DRC verification expertise
High-quality custom layout design delivery

Good to have:

Scripting languages (Python, TCL)
Parasitic extraction and analysis knowledge
Layout verification tools and methodologies
Reliability and manufacturability awareness
Strong communication and teamwork skills

Perks:

Bonus
Equity
Benefits

Minimum qualifications:

Bachelor's degree in Electrical Engineering or a related field, or equivalent practical experience.
8 years of experience with analog circuit design principles and layout techniques.
Experience with industry-standard layout tools (e.g., Cadence Virtuoso, Mentor Graphics Calibre).
Experience with advanced process nodes (22nm and below) and associated design challenges.

Preferred qualifications:

Experience with scripting languages (e.g., Python, TCL) for layout automation.
Knowledge of parasitic extraction and analysis.
Familiarity with various layout verification tools and methodologies.
Familiarity with reliability and manufacturability considerations.
Strong communication and teamwork abilities.
Excellent problem-solving and analytical skills.

About the job

Google engineers develop the next-generation technologies that change how users connect, explore, and interact with information and one another. As a member of an extraordinarily creative, motivated and talented team, you develop new products that are used by millions of people. We need our engineers to be versatile and passionate to take on new problems as we continue to push technology forward. If you get excited about building new things and working across discipline lines, then our team might be your next career step.

As a Silicon Layout Engineer you will be delivering high-performance analog layout design, performing various verification checks, participating in full-chip layout verification, and developing efficient methodology.

Google's Raxium display group has established a revolutionary semiconductor materials display technology that enables new functionality in display products, bringing to users a closer and more natural linkage between the digital and physical realms in applications such as augmented reality (AR) and light-field display. With start-up roots and a state-of-the-art compound semiconductor fab in Silicon Valley, Raxium is seeking to build upon its engineering team with an aim to disrupt next-generation display markets.

The US base salary range for this full-time position is $177,000-$266,000 + bonus + equity + benefits. Our salary ranges are determined by role, level, and location. The range displayed on each job posting reflects the minimum and maximum target for new hire salaries for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.

Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about .

Responsibilities

Deliver high-quality custom layout designs for complex analog modules targeting advanced process nodes (22nm and below).
Collaborate closely with circuit designers to understand design specifications and constraints, ensuring layout implementations meet performance targets.
Utilize advanced layout techniques to optimize for area, performance, and power, while adhering to stringent design rules.
Perform comprehensive verification checks, including but not limited to: Layout Versus Schematic (LVS) verification to ensure accurate circuit representation and Design Rule Checking (DRC) to comply with foundry manufacturing requirements.
Contribute to the development and improvement of layout methodologies and best practices.

View Full Job Description

$177.0K - $266.0K/yr (Outscal est.)

$221.5K/yr avg.

Worldwide

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About The Company

Google

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A problem isn't truly solved until it's solved for all. Googlers build products that help create opportunities for everyone, whether down the street or across the globe. Bring your insight, imagination and a healthy disregard for the impossible. Bring everything that makes you unique. Together, we can build for everyone.