ASIC Design Verification Engineer
About the job
SummaryBy Outscal
About the job:
As a Design Verification Engineer at Google, you will be part of a team developing custom silicon solutions for direct-to-consumer products. You will collaborate with design and verification engineers on active projects, performing verification using your expertise in SystemVerilog coding and problem-solving skills. You will build constrained-random verification environments that exercise designs through their corner-cases and expose all types of bugs. Your responsibilities will encompass the full verification life cycle, from planning to execution, collecting and closing coverage. You will plan the verification of complex digital design blocks, debug tests with design engineers, and enhance constrained-random verification environments using SystemVerilog and UVM. You will also identify and write all types of coverage measures for stimulus and corner-cases.
Must have:
- Bachelor's degree in Computer Science, Electrical Engineering or related field
- Experience with SystemVerilog
- SystemVerilog Assertions or functional coverage experience
Good to have:
- Master's degree or PhD in Electrical Engineering
- Experience with Universal Verification Methodology (UVM)
- Experienced with the full verification life cycle
Perks:
- Bonus
- Equity
- Benefits
Minimum qualifications:
- Bachelor's degree in Computer Science, Electrical Engineering, a related field, or equivalent practical experience.
- Experience with SystemVerilog (i.e., SystemVerilog Assertions or functional coverage).
Preferred qualifications:
- Master's degree or PhD in Electrical Engineering.
- Experience with Universal Verification Methodology (UVM).
- Experienced with the full verification life cycle.
About the job
Be part of a diverse team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You will contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
As a Design Verification Engineer you will use your design and verification experience to verify digital designs. You will collaborate with design and verification engineers in active projects and perform verification. Using your SystemVerilog coding and problem-solving skills, you will build efficient and effective constrained-random verification environments that exercise designs through their corner-cases and expose all types of bugs. You will be responsible for the full life cycle of verification, from verification planning to test execution, to collecting and closing coverage.
Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.The US base salary range for this full-time position is $127,000-$187,000 + bonus + equity + benefits. Our salary ranges are determined by role, level, and location. The range displayed on each job posting reflects the minimum and maximum target salaries for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.
Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about .
Responsibilities
- Plan the verification of complex digital design blocks by fully understanding the design specification and interacting with design engineers to identify important verification scenarios.
- Debug tests with design engineers to deliver functionally correct design blocks.
- Create and enhance constrained-random verification environments using SystemVerilog and Universal Verification Methodology (UVM), or formally verify designs with SystemVerilog Assertions (SVA) and formal tools.
- Identify and write all types of coverage measures for stimulus and corner-cases.
View Full Job Description
$127.0K - $187.0K/yr (Outscal est.)
$157.0K/yr avg.
Sunnyvale, California, United States
About The Company
A problem isn't truly solved until it's solved for all. Googlers build products that help create opportunities for everyone, whether down the street or across the globe. Bring your insight, imagination and a healthy disregard for the impossible. Bring everything that makes you unique. Together, we can build for everyone.
