ASIC Design Engineer, RTL, Silicon
Job Summary
Job Description
- 3+ years ASIC design experience
- Verilog/SystemVerilog proficiency
- ASIC design methodologies knowledge
- RTL coding, simulation, and debugging skills
- Collaboration with cross-functional teams
- Master's/PhD in Electrical Engineering
- Experience with chip design flow
- STA closure, DV test-plan review
- Knowledge of processor cores, interconnects, security etc.
3 skills required
Job Details
Minimum qualifications:
- Bachelor's degree in Electrical Engineering, Computer Science, or equivalent practical experience.
- 3 years of experience in design, multi-power domains with clocking, and SoCs with silicon.
- Experience with Verilog or SystemVerilog language.
- Experience with ASIC design methodologies for front quality checks including Lint, CDC/RDC, Synthesis, DFT ATPG/Memory BIST, UPF and Low Power Estimation.
Preferred qualifications:
- Master's degree or PhD in Electrical Engineering or equivalent practical experience.
- Experience with chip design flow and cross-domain involving DV, DFT, Physical Design, software.
- Experience in STA closure, DV test-plan review and coverage analysis of the sub-system and chip level verification.
- Knowledge in one or more of these areas: Processor Cores, Interconnects, Debug and Trace, Security, Interrupts, Clocks/Reset, Power/Voltage Domains, Pin-muxing.
About the job
Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.
Responsibilities
- Define the microarchitecture of IPs, Subsystems or SOCs and work with the team to deliver a quality, schedule compliant and PPA optimized design.
- Work with the cross-functional team of Verification, Design for Test, Physical Design and Software teams to make design decisions and represent project status throughout the development process.
- Define the block level design document such as interface protocol, block diagram, transaction flow, pipeline, etc.
- Perform RTL coding for SS/SOC integration, function/performance simulation debug, Lint/CDC/FV/UPF checks.
- Work with key design collaterals such as SDC and UPF, and with stakeholders to negotiate the right collateral quality and identify solutions.
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About The Company
A problem isn't truly solved until it's solved for all. Googlers build products that help create opportunities for everyone, whether down the street or across the globe. Bring your insight, imagination and a healthy disregard for the impossible. Bring everything that makes you unique. Together, we can build for everyone.
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