ASIC Design Verification Engineer
Job Summary
Job Description
- Bachelor's degree in relevant field
- 2+ years experience with industry standard tools
- SystemVerilog and functional coverage experience
- Experience in design verification
- Problem-solving and debugging skills
- Master's degree in relevant field
- 6+ years experience in design verification
- UVM testbenches and methodologies experience
- Test plan development and execution experience
- Bonus
- Equity
- Benefits
2 skills required
Job Details
Minimum qualifications:
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
- 2 years of experience with industry standard tools, languages and methodologies relevant to the development of silicon-based ICs and chips.
- Experience with SystemVerilog (i.e., SystemVerilog Assertions or functional coverage).
Preferred qualifications:
- Master's degree in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture, or a related field.
- 6 years of experience in design verification.
- Experience with UVM testbenches and methodologies.
- Experience developing and executing test plans.
- Excellent problem-solving and debugging skills.
About the job
In this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.
As an ASIC Design Verification Engineer, you will be part of a team developing ASICs to accelerate computation in data centers. You will be responsible in areas such as project definition, design verification, and silicon bringup. You will participate in the architecture, documentation, and verification of the next generation of data center accelerators.
The Machine Learning (ML), Systems, and Cloud AI (MSCA) organization at Google designs, implements, and manages the hardware, software, machine learning, and systems infrastructure for all Google services (Search, YouTube, etc.) and Google Cloud. Our end users are Googlers, Cloud customers and the billions of people who use Google services around the world.
We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including Google Cloud’s Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers.
The US base salary range for this full-time position is $132,000-$189,000 + bonus + equity + benefits. Our salary ranges are determined by role, level, and location. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.
Responsibilities
- Plan the verification of complex digital design blocks, understand the design specification, and interact with design engineers to identify important verification scenarios.
- Create a constrained-random verification environment using SystemVerilog and Universal Verification Methodology (UVM).
- Identify and write all types of coverage measures for stimulus and corner-cases.
- Debug tests with design engineers to deliver correct design blocks.
- Close coverage measures to identify verification holes and to show progress towards tape-out.
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