As a CPU Integration CAD Engineer, you'll play a key role in floor-planning, physical design, and verification for Qualcomm's Oryon CPU cores. You'll develop and maintain flows and methodologies for building industry-leading silicon with exceptional performance and efficiency.
Must have:
Physical Design
Floor Planning
PDV Analysis
Python/Tcl
Good to have:
Methodology Improvement
Place-and-Route
Advanced Technology Nodes
EDA Tools
Perks:
Cross-Functional Teams
Industry-Leading Silicon
About the job
Company Qualcomm India Private Limited Job Area Engineering Group, Engineering Group > Hardware Engineering General Summary NUVIA is now part of Qualcomm. Our mission is to reimagine silicon and create computing platforms that will transform the industry. You will have the opportunity to work with some of the most talented and passionate engineers in the world to create designs that push the envelope on performance, energy efficiency and scalability. Minimum Qualifications
Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience.
OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 5+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. As CPU Integration CAD engineer, you will enable the floor-planning, physical design (PD), physical design verification (PDV), and signoff of Qualcomm’s class-leading Oryon CPU cores. You will build and support agile flows and methodologies that enable the first time right development of products with industry-leading power, performance and area. Roles and Responsibilities
Work closely with worldwide cross-functional teams such as CPU physical design, CPU and SOC Integration, Technology and Central CAD
Develop, integrate and release flows and methodologies for floor planning, power planning, pin placement, chip assembly, PDV analysis
Develop and maintain unit and system tests to enable correct-by-construction floorplans and physical layouts
Architect and recommend methodology improvements to ensure our silicon has the best power, performance and area
Maintain and support implementation flows, and resolve project-specific issues
Work with EDA vendors to define roadmap and to resolve tool issues
Preferred Qualifications
Bachelors/Masters degree in Electrical/Electronics Engineering or Computer Science
Ten+ years of hands-on experience in development of high-performance chips - either in a design or CAD role
High level of programming proficiency (Python and Tcl). Knowledge of data structures and algorithms
Experience with automation
Experience with a broad variety of Physical Design tasks - ranging all the way from place-and-route, analysis, timing sign-off and PDV
Experience with advanced technology nodes (5nm or lower)
Strong user of industry-standard PDV tools such as Siemens/Mentor Calibre
Strong user of industry-standard place-and-route tools such as Cadence Innovus
Proven track record of managing and regressing place-and-route flows
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