DMTM self-sustaining (DSS) Collateral-Device Engineers are the pioneers responsible for enabling and sustaining Collateral functions (Design rules, Generator/DFM, Frame layout, Param design/etest, and TCAD) in HVM manufacturing independently. The Engineers are responsible to link fab process teams and design team seamlessly with highly effective business procedures established. The Engineers need to handshake with design team on design update, and work closely with collateral litho team on mask layer generation, DFM, frame layout edits, and reticle tape out based on process needs. The Engineers are also expected to work closely with fab teams (PI/PO/YE etc) to improve Yield/Reliability/ DPM, address excursions, and lead/support TF/WGs. The engineers are also expected to lead scientific research enabling manufacture of innovative device architectures coupled with the Designing, executing and analyzing experiments necessary to meet engineering specifications.
The position is associated with the sale of the NAND business to SK Hynix aligning to Phase 2 of the transaction. Employees aligned to Phase 2 will continue to be employed by Intel developing NAND technology and components. Phase 2 of the transaction is expected to close in March 2025 at which time employees aligned to this phase of the transaction will transition employment to Solidigm, a stand-alone US subsidiary of SK Hynix headquartered in San Jose, California with offices world-wide. Solidigm is a leading global supplier of NAND flash memory solutions, led by Robert (Rob) B. Crooke as CEO, previously senior vice president and general manager of Intel's Non-Volatile Memory Solutions Group
Minimum Qualifications:
Candidate must possess a PhD or Masters degree with experience in a relevant field such as Electrical Engineering, Materials Science and Engineering, Chemical Engineering, Physics or other similar technical degree.
Preferred Qualifications: Experience in the following: Logic process integration or device engineering Param analysis, report, NAND process integration engineering. Familiar with process characterization, qualification, troubleshooting and probe yield improvement Familiar with characterization techniques such as SEM, TEM, EDX, SIMS etc. Statistical design of experiments, SPC, PCS methodology, data analysis skills and experience with JMP, SQL PF, Python, Catalyst etc. In-depth knowledge of device physics, parametric test structures, and probe sort data. Familiar with CAD tools and software for test structure layout review Hands-on experiences in technology development, technology transfer and/or technology startup. Strong commitment in work and flexible in working time
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