IP Logic Designer Engineer

4 Days ago • 1 Years + • $121,050 PA - $170,890 PA

Job Summary

Job Description

The IP Logic Designer Engineer will be responsible for developing logic design, RTL coding, and simulation for an IP required to generate cell libraries, functional units, IP blocks, and subsystems. They will participate in the definition of architecture and microarchitecture features, optimize logic, and ensure design integrity. They will also review verification plans, resolve RTL test failures, and support SoC customers. The role involves ensuring high-quality integration and verification of the IP block. This position is within the Data Center & Artificial Intelligence Group (DCAI) at Intel, which focuses on cloud, communications, enterprise, and government data centers.
Must have:
  • Bachelor's Degree in Electrical Engineering with 1+ years uArch design.
  • Proficient in RTL coding.
  • Ability to debug and root cause pre-silicon validation failures quickly.
  • Knowledge in static tool failures and how to fix them in RTL
Good to have:
  • Knowledge in timing reports and how to resolve timing failures in RTL.
  • Silicon debug experience.
  • Modern energy-efficient/low-power logic design techniques.
Perks:
  • Competitive pay.
  • Stock.
  • Bonuses.
  • Health, retirement, and vacation benefits.

Job Details

Job Details:

Job Description: 

Do Something Wonderful!

Intel put Silicon in Silicon Valley. No one else is obsessed with engineering and have a brighter future. Every day, we create world changing technology that enriches the lives of every person on earth. So, if you have a big idea, let's do something wonderful together. Join us, because at Intel, we are building a better tomorrow.

Who We Are

I/O Memory Management Unit (IOMMU) IP is an integral part of Client and Server products, which enables I/O Virtualization (Intel VT-d) on Intel platforms. In today’s AI-focused datacenters and personal computing platforms, there is a renewed focus on improving the power, performance of I/O workloads, and security between different execution contexts. IOMMU plays a critical role in all of this.

Who You Are

Responsibilities include but are not limited to:

  • Develops the logic design, register transfer level (RTL) coding, and simulation for an IP required to generate cell libraries, functional units, IP blocks, and subsystems for integration in full chip designs.

  • Participates in the definition of architecture and microarchitecture features of the block being designed.

  • Applies various strategies, tools, and methods to write RTL and optimize logic to qualify the design to meet power, performance, area, and timing goals as well as design integrity for physical implementation.

  • Reviews the verification plan and implementation to ensure design features are verified correctly and resolves and implements corrective measures for failing RTL tests to ensure correctness of features.

  • Supports SoC customers to ensure high quality integration and verification of the IP block. Drives quality assurance compliance for smooth IPSoC handoff.

Qualifications:

You must possess the minimum education requirements and minimum required qualifications to be initially considered for this position. Relevant experience can be obtained through schoolwork, classes, project work, internships, and/or military experience. Additional preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.
 

Minimum Qualifications

  • Bachelor’s Degree in Electrical Engineering with 1+ Years of uArch design and MAS Development to HAS and Master’s Degree in Electrical Engineering

  • Proficient in RTL coding

  • Must be able to debug and root cause pre-silicon volume validation failures quicky

  • Knowledge in static tool failures and how to fix them in RTL

Preferred Qualifications

  • Knowledge in timing reports and how to resolve timing failures in RTL

  • Silicon debug experience

  • Modern energy-efficient/low-power logic design techniques, including those specifically applicable to high frequency optimization.

          

Job Type:

Experienced Hire

Shift:

Shift 1 (United States of America)

Primary Location: 

US, Oregon, Hillsboro

Additional Locations:

Business group:

The Data Center & Artificial Intelligence Group (DCAI) is at the heart of Intel’s transformation from a PC company to a company that runs the cloud and billions of smart, connected computing devices. The data center is the underpinning for every data-driven service, from artificial intelligence to 5G to high-performance computing, and DCG delivers the products and technologies—spanning software, processors, storage, I/O, and networking solutions—that fuel cloud, communications, enterprise, and government data centers around the world.

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

N/A

Benefits:

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation.  Find more information about all of our Amazing Benefits here:

https://intel.wd1.myworkdayjobs.com/External/page/1025c144664a100150b4b1665c750003

Annual Salary Range for jobs which could be performed in the US:

$121,050.00-$170,890.00

Salary range dependent on a number of factors including location and experience.

Work Model for this Role

This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.

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