Memory Layout Engineer

1 Hour ago • All levels

Job Summary

Job Description

The Memory Layout Engineer will lead the design and development of memory layouts for complex ICs, specializing in high-density SRAM memories and specialty memory blocks. This role involves defining memory architecture, developing layout techniques for low-power and high-speed design, and collaborating with design and verification teams. Responsibilities include mentoring junior engineers, staying updated on memory design trends, performing physical verification using DRC, DSM, LVS, and other tools, driving Design for Manufacturability (DFM) and Design for Yield (DFY) initiatives, and analyzing layouts for power and signal integrity issues. The engineer may also be involved in scripting automation for layout tasks using languages like PERL, Shell, TCL, or Skill.
Must have:
  • Experience on Memory layout-MRAM/RRAM/SRAM/CAM/TCAM
  • Define memory architecture and sub-block specifications
  • Develop advanced layout techniques for low-power, high-speed design
  • Perform physical verification using DRC, DSM, LVS, and other tools

Job Details

Company Description

Spruce InfoTech, a leading IT firm, offers innovative and cost-effective solutions to help clients manage and transform their businesses. Our services are designed to guide companies of all sizes, from small businesses to Fortune 500 organizations, in maximizing their IT investment while reducing technology costs. Our team of experts has extensive technical knowledge in enterprise solutions, which helps organizations transform these solutions into a strategic asset that can drive new revenue and improve business operations.

Website

http://www.spruceinfotech.com

    Job Description

    Job Title-   Memory Layout Engineer

    Location –  Ottawa, ON – Canada

    Contract – 1+ year  

     

     

    Memory Layout Engineer:
    ( Experience on Memory layout-MRAM/RRAM/SRAM/CAM/TCAM,  Memory compiler/Tiler, complex memory layout, define and architect , floor planning of memory, low power and high speed and high density , sense amplifier layout, decoder layout , memory peripheral layout,  CADENSE -virtuso tool, collaborate memory circuit designer and memory verification engineer
    Responsibilities

    • Lead the design and development of memory layouts for complex ICs, including:
    • High-density SRAM memories
    • Specialty memory blocks (e.g., memory, CAM)
    • Define memory architecture and sub-block specifications
    • Develop and implement advanced layout techniques for low-power, high-speed memory design
    • Collaborate with design and verification teams to ensure seamless integration
    • Mentor junior engineers and provide technical guidance
    • Stay up-to-date on the latest memory design trends and technologies
    • Perform comprehensive physical verification- follow the design rules given by foundry( example) metal density, space etc) using DRC, DSM, LVS, and other tools
    • Drive Design for Manufacturability (DFM) and Design for Yield (DFY) initiatives
    • Analyze layouts for potential power integrity and signal integrity issues
    • May involve scripting automation for layout tasks using languages like PERL, Shell, TCL, or Skill
    • Non Volatile / Volatile -Memory

     

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