RTL Design Engineer, Core-IP

This role involves RTL design development of audio and security IPs and subsystems for Google's direct-to-consumer products. Responsibilities include microarchitecture development, Verilog/SystemVerilog RTL coding, simulation and debugging, low power design, meeting power, performance, and area targets, participating in synthesis and timing closure, pre/post-silicon bring-up, test planning, coverage analysis, and creating automation tools. The ideal candidate will have experience with ASIC design methodologies and QA flows (Lint, CDC, RDC, VCLP), and experience with scripting languages like Perl or Python. The position requires collaboration with architects and contributions to high-quality, optimized security designs.