Job Details:

Job Description: 

Join Intel and seize the opportunity to innovate and expand computing technology, connecting and enriching the lives of every person on Earth. As a DTCO (Design Technology Co-Optimization) engineer, you will engage in all aspects of the SoC design flow, from high-level design to synthesis, place and route, timing, and power, to create optimal designs.

As a DTCO APR engineer, your responsibilities will include, but are not limited to:

• Supporting RTL synthesis and conducting place and route experiments using both internal and external vendor tools to enhance Intel's product Power, Performance, and Area (PPA) for current and future process nodes on internal Intel Architecture (IA/X86) and external ARM IPs.
• Managing changes in floorplan, corresponding scaling, and assessing their impact on power, congestion, and timing for the current technology node, while predicting their effects on power, routing, and timing scaling for the next technology node.
• Improving cell utilization and transistor density metrics by leveraging cutting-edge tools and methodologies.
• Analyzing power (dynamic and leakage), performance (setup and hold), enhancing critical path timing, reducing congestion by optimizing the use of available metal layers, debugging tools, and more.

Qualifications:

• Bachelor's Degree (Master's Degree preferred) in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
• 5+ years of relevant experience in silicon design and/or TFM development.

Experience in the following areas:

• Proficiency in at least one of the following: Python, Perl, TCL, Shell scripting.
• Use of industry-standard placement and routing CAD tools.
• Proven track record in Si Tape Out.

Preferred Qualifications:

• Experience in floor planning and power grid setup, clock methodologies, IR droop and SI mitigation strategies, power and timing signoff conditions, and leveraging industry-standard tools, flows, and methodologies to achieve optimal PPA tradeoffs.
• Experience in feasibility studies or technology pathfinding.
• Experience in more than one ASIC Digital Implementation TFM ( SNPS / CDNS / Others ).
• Background in Artificial Intelligence and Machine Learning (AI-ML).

#DesignEnablement #DesignTechnologyPlatform

          

Job Type:

Experienced Hire

Shift:

Shift 1 (Malaysia)

Primary Location: 

Malaysia, Penang

Additional Locations:

Business group:

As the world's largest chip manufacturer, Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support.  Employees in the Technology Development and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore’s Law to bring smart, connected devices to every person on Earth.

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

N/A

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.