Hardware Architecture Modeling Engineer, Accelerators
Job Summary
Job Description
- Bachelor's degree in relevant field or equivalent experience
- 3+ years experience in computer architecture performance analysis
- C++ software development experience
- Workload performance analysis and benchmarking
- Collaboration with hardware and software teams
- Experience in applying computer architecture principles
- Hardware and software co-design experience
- Python development experience
- Knowledge of processor/accelerator design and ML model mapping
- RTL design using Verilog
3 skills required
Job Details
Minimum qualifications:
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
- 3 years of experience in computer architecture performance analysis and optimization, or a PhD degree.
- Experience in developing software systems in C++.
Preferred qualifications:
- Experience in applying computer architecture principles to solve open-ended problems.
- Experience in analyzing workload performance and creating benchmarks.
- Experience in hardware and software co-design.
- Experience with developing in Python.
- Knowledge of processor design or accelerator designs and mapping ML models to hardware architectures.
- Knowledge of design of digital reasoning at the Register Transfer Level (RTL) using Verilog.
About the job
In this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a diverse team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.
In this role, you will work with hardware and software architects to model, analyze, and define next-generation Tensor Processing Unit (TPUs).
The ML, Systems, & Cloud AI (MSCA) organization at Google designs, implements, and manages the hardware, software, machine learning, and systems infrastructure for all Google services (Search, YouTube, etc.) and Google Cloud. Our end users are Googlers, Cloud customers and the billions of people who use Google services around the world.We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including Google Cloud’s Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers.
Responsibilities
- Work on Machine Learning (ML) workload characterization and benchmarking.
- Conduct performance and power analysis and evaluate proposals.
- Develop architectural and microarchitectural models to enable quantitative analysis.
- Collaborate with partners in hardware design, software, compiler, Machine Learning (ML) model and research teams for hardware/software co-design.
- Propose capabilities and optimizations for next-generation TPUs and chip roadmap.
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About The Company
A problem isn't truly solved until it's solved for all. Googlers build products that help create opportunities for everyone, whether down the street or across the globe. Bring your insight, imagination and a healthy disregard for the impossible. Bring everything that makes you unique. Together, we can build for everyone.
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