Senior Design Verification Engineer, Multimedia, Silicon

Minimum qualifications:

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
• 5 years of experience verifying digital logic at Register-Transfer Level (RTL) using System Verilog for Application-Specific Integrated Circuit (ASICs).
• Experience verifying digital systems using standard IP components/interconnects (e.g., microprocessor cores, hierarchical memory subsystems).
• Experience with object oriented programming.

Preferred qualifications:

• Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture, or a related field.
• Experience creating and using verification components and environments in a standard verification methodology such as Universal Verification Methodology (UVM).
• Experience with image processing or other multimedia Intellectual Property (IPs) such as display or video codec.
• Experience with performance verification of ASICs and ASIC components and experience with ASIC standard interfaces and memory system architecture.
• Experience with verification techniques, System Verilog Assertions (SVA) and assertion-based verification.
• Experience with GLS, low-power DV, and support of SOC DV.