Senior Staff Verification Engineer

6575 Years ago • 6 Years + • Research & Development

About the job

Job Description

Marvell seeks a Senior Staff Verification Engineer with 6+ years of experience in UVM, Verilog, System Verilog, and scripting languages. The role involves developing and maintaining verification environments, defining test plans, and driving verification coverage. Experience with PCIe, NVMe, AXI, and AHB is a plus.
Must have:
  • UVM experience
  • Verilog/SystemVerilog
  • Scripting languages
  • Verification experience
Good to have:
  • PCIe experience
  • NVMe experience
  • AXI/AHB knowledge
  • Test plan definition
Perks:
  • Competitive compensation
  • Great benefits
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About Marvell

Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, automotive, and carrier architectures, our innovative technology is enabling new possibilities. 

At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. 

Your Team, Your Impact

Marvell is a leading provider of innovative storage technologies, including ultra‐fast read channels, high‐performance processors, leading edge transceivers, highly efficient analog designs, and powerful cryptographic engines. These solutions address all segments of the hard disk drive (HDD) and solid state drive (SSD) electronics markets. Many of the same technologies have been utilized in Marvell storage system solutions products, powering PCs, servers, cloud, and enterprise systems.

What You Can Expect

  • Develop and maintain verification environment in UVM (Universal Verification Methodology)
  • Define and review verification test plan with architecture team and design team
  • Verify the design with directed and constraint random functional parameters
  • Maintain regression and debug test failures with designers
  • Report and analyze verification coverage of design features and parameters
  • Drive the verification to reach coverage target
  • Take responsibility in the verification of blocks, sub-systems and top-level environment.

What We're Looking For

  • Bachelor’s/Master's/PhD in Computer Science, Electrical Engineering or related fields and 6+ years of related professional experience.
  • Hands-on experience on using Verilog, System Verilog and UVM (Universal Verification Methodology)
  • Good scripting skills in languages such as Perl, Tcl, or Python.
  • Experience in PCIe and NVMe is a plus
  • Knowledge of AXI and AHB is a plus
  • Good verbal and written communication skills in English.

Additional Compensation and Benefit Elements

With competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We’re dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what it’s like to work at Marvell, visit our Careers page.

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.

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About The Company

Pavia, Lombardy, Italy (On-Site)

Pavia, Lombardy, Italy (On-Site)

Pavia, Lombardy, Italy (On-Site)

Pavia, Lombardy, Italy (On-Site)

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Ho Chi Minh City, Ho Chi Minh City, Vietnam (On-Site)

Yokne'am Illit, North District, Israel (On-Site)

Irvine, California, United States (Hybrid)

Singapore (On-Site)

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