Silicon RTL IP/Subsystem Senior Engineer
Job Summary
Job Description
This senior engineering role at Google Cloud involves designing and implementing custom silicon solutions for direct-to-consumer products and data center accelerators. Responsibilities include owning the microarchitecture and implementation of IPs and subsystems, collaborating with cross-functional teams (architecture, firmware, software, verification, physical design), driving design methodology and improvements, and identifying opportunities for power, performance, and area optimization. The ideal candidate will have extensive experience in ASIC development using Verilog/SystemVerilog or VHDL, as well as experience with design verification, synthesis, timing/power analysis, and DFT. The role contributes to accelerating machine learning computation in Google's data centers.
Must have:
- 5+ years ASIC development experience
- Verilog/SystemVerilog or VHDL expertise
- ASIC design verification, synthesis, timing/power analysis, DFT
- Micro-architecture and IP/subsystem design
- Collaboration with cross-functional teams
Good to have:
- Python or Perl coding experience
- SoC design and integration experience
- Knowledge of arithmetic units, bus architectures, processor design, accelerators, or memory hierarchies
- High-performance and low-power design techniques
3 skills required
Job Details
Minimum qualifications:
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience
- 5 years of experience in Application-specific integrated circuit (ASIC) development with Verilog/SystemVerilog, Vhsic Hardware Description Language (VHDL), or Chisel.
- Experience in ASIC design verification, synthesis, timing/power analysis, and Design for Testing (DFT).
- Experience in micro-architecture and designing IPs and subsystems.
Preferred qualifications:
- Experience with coding languages (e.g., Python or Perl).
- Experience in System on a Chip (SoC) designs and integration flows.
- Knowledge of arithmetic units, bus architectures, processor design, accelerators, or memory hierarchies.
- Knowledge of high performance and low power design techniques.
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.In this role, you will be part of a team developing Application-specific integrated circuit (ASICs) used to accelerate machine learning computation in data centers. You will collaborate with members of architecture, verification, power and performance, physical design, etc to specify and deliver quality designs for next generation data center accelerators. You will solve technical problems with micro-architecture and practical reasoning solutions, and evaluate design options with complexity, performance, power.The ML, Systems, & Cloud AI (MSCA) organization at Google designs, implements, and manages the hardware, software, machine learning, and systems infrastructure for all Google services (Search, YouTube, etc.) and Google Cloud. Our end users are Googlers, Cloud customers and the billions of people who use Google services around the world.
We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including Google Cloud’s Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers.
Responsibilities
- Own microarchitecture and implementation of Internet Protocol (IPs) and subsystems.
- Work with Architecture, Firmware, and Software teams to drive feature closure and develop microarchitecture specifications.
- Drive design methodology, libraries, debug, code review in coordination with other Internet Protocol (IPs) Design Verification (DV) teams and physical design teams.
- Identify and drive power, performance and area of improvements.
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