Analog Mixed Signal Design Verification
Job Summary
Job Description
Lead AMS DV for a hardware startup designing RiscV-based chiplets. Must have strong UVM, SystemVerilog, and mixed-signal verification experience. Experience with assertion-based verification and power-aware verification is a plus.
Must have:
- UVM Testbenches
- SystemVerilog
- Mixed-Signal
- Assertion Based
Good to have:
- Power Aware
- UPF
- UVM-AMS
- SV-Real
Perks:
- Hardware Startup
- RiscV Chiplets
4 skills required
Job Details
Join a well funded hardware startup as an AMS DV engineer leading the design verification for droop sensing, clocking, PLL, LDO, On-die VRs and PMICs using latest finfet technology nodes. Our mission is to reimagine silicon and disrupt the high performance computing platforms with the RiscV based chiplet designs.
Responsibilities
- Responsible for performing verification for AMS designs.
- Create UVM benches for mixed signal blocks and developing test scenarios.
- Work closely with the architecture and design teams on verification plan and methodology to achieve complete verification coverage
- Write assertions and checkers for the properties and corner cases
- Analyze verification coverage and improve the test cases
- Integrate analogue design IPs from vendors and internal teams and develop verification environments for simulation and emulation
Requirements
- Detailed knowledge of verification using SystemVerilog
- Experience with creating UVM based testbenches for Analog Mixed-Signal applications
- Experience with assertion based verification for analog blocks
- Experience with power aware verification with UPF will be a plus
- UVM-AMS experience preferred
- Experience with sv-real preferred
- Scripting skills in perl / python is preferred
- Excellent communication skills
- Team player with an ability to encourage team members
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