This role involves planning and executing verification of next-generation configurable infrastructure IPs, interconnects, and memory subsystems. Responsibilities include creating and enhancing constrained-random verification environments using SystemVerilog and UVM, developing cross-language tools and verification methodologies, identifying and writing coverage measures, and debugging tests with design engineers. The ideal candidate will have experience verifying digital logic at the RTL level using SystemVerilog or C/C++, experience with standard verification methodologies and IP components (microprocessor cores, memory subsystems), and proficiency in scripting languages and software development frameworks. The position contributes to the innovation behind Google's direct-to-consumer products, shaping the next generation of hardware experiences.